diff --git a/gcc/common/config/arm/arm-common.c b/gcc/common/config/arm/arm-common.c
index 93a13c8..79e3f1f 100644
--- a/gcc/common/config/arm/arm-common.c
+++ b/gcc/common/config/arm/arm-common.c
@@ -107,12 +107,12 @@ struct arm_arch_core_flag
 static const struct arm_arch_core_flag arm_arch_core_flags[] =
 {
 #undef ARM_CORE
-#define ARM_CORE(NAME, X, IDENT, TUNE_FLAGS, ARCH, FLAGS, COSTS) \
+#define ARM_CORE(NAME, X, IDENT, TUNE_FLAGS, ARCH, ISA, FLAGS, COSTS)	\
   {NAME, FLAGS},
 #include "config/arm/arm-cores.def"
 #undef ARM_CORE
 #undef ARM_ARCH
-#define ARM_ARCH(NAME, CORE, TUNE_FLAGS, ARCH, FLAGS)	\
+#define ARM_ARCH(NAME, CORE, TUNE_FLAGS, ARCH, ISA, FLAGS)	\
   {NAME, FLAGS},
 #include "config/arm/arm-arches.def"
 #undef ARM_ARCH
diff --git a/gcc/config/arm/arm-arches.def b/gcc/config/arm/arm-arches.def
index d81a471..02ece42 100644
--- a/gcc/config/arm/arm-arches.def
+++ b/gcc/config/arm/arm-arches.def
@@ -19,50 +19,50 @@
 
 /* Before using #include to read this file, define a macro:
 
-      ARM_ARCH(NAME, CORE, TUNE_FLAGS, ARCH, FLAGS)
+      ARM_ARCH(NAME, CORE, TUNE_FLAGS, ARCH, ISA, FLAGS)
 
    The NAME is the name of the architecture, represented as a string
    constant.  The CORE is the identifier for a core representative of
-   this architecture.  ARCH is the architecture revision.  FLAGS is
-   the set of feature flags implied by the architecture.
+   this architecture.  ARCH is the architecture revision.  ISA is the
+   detailed architectural capabilities of the core (see arm-isa.h).
+   FLAGS is the set of feature flags implied by the architecture.
 
    genopt.sh assumes no whitespace up to the first "," in each entry.  */
 
-ARM_ARCH("armv2",   arm2,       (TF_CO_PROC | TF_NO_MODE32), 2,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2))
-ARM_ARCH("armv2a",  arm2,       (TF_CO_PROC | TF_NO_MODE32), 2,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2))
-ARM_ARCH("armv3",   arm6,       TF_CO_PROC, 3,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3))
-ARM_ARCH("armv3m",  arm7m,      TF_CO_PROC, 3M,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3M))
-ARM_ARCH("armv4",   arm7tdmi,   TF_CO_PROC, 4,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4))
+ARM_ARCH("armv2",   arm2,       (TF_CO_PROC | TF_NO_MODE32), 2,		ISA_FEAT(ISA_ARMv2) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2))
+ARM_ARCH("armv2a",  arm2,       (TF_CO_PROC | TF_NO_MODE32), 2,		ISA_FEAT(ISA_ARMv2) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2))
+ARM_ARCH("armv3",   arm6,       TF_CO_PROC,   		     3,		ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3))
+ARM_ARCH("armv3m",  arm7m,      TF_CO_PROC, 		     3M,	ISA_FEAT(ISA_ARMv3m) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3M))
+ARM_ARCH("armv4",   arm7tdmi,   TF_CO_PROC, 		     4,		ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4))
 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
    implementations that support it, so we will leave it out for now.  */
-ARM_ARCH("armv4t",  arm7tdmi,   TF_CO_PROC, 4T,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T))
-ARM_ARCH("armv5",   arm10tdmi,  TF_CO_PROC, 5,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5))
-ARM_ARCH("armv5t",  arm10tdmi,  TF_CO_PROC, 5T,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5T))
-ARM_ARCH("armv5e",  arm1026ejs, TF_CO_PROC, 5E,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5E))
-ARM_ARCH("armv5te", arm1026ejs, TF_CO_PROC, 5TE,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE))
-ARM_ARCH("armv6",   arm1136js,  TF_CO_PROC, 6,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6))
-ARM_ARCH("armv6j",  arm1136js,  TF_CO_PROC, 6J,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6J))
-ARM_ARCH("armv6k",  mpcore,	TF_CO_PROC, 6K,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6K))
-ARM_ARCH("armv6z",  arm1176jzs, TF_CO_PROC, 6Z,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6Z))
-ARM_ARCH("armv6kz", arm1176jzs, TF_CO_PROC, 6KZ,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6KZ))
-ARM_ARCH("armv6zk", arm1176jzs, TF_CO_PROC, 6KZ,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6KZ))
-ARM_ARCH("armv6t2", arm1156t2s, TF_CO_PROC, 6T2,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6T2))
-ARM_ARCH("armv6-m", cortexm1,	0,	      6M,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M))
-ARM_ARCH("armv6s-m", cortexm1,	0,	      6M,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M))
-ARM_ARCH("armv7",   cortexa8,	TF_CO_PROC, 7,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7))
-ARM_ARCH("armv7-a", cortexa8,	TF_CO_PROC, 7A,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A))
-ARM_ARCH("armv7ve", cortexa8,	TF_CO_PROC, 7A,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7VE))
-ARM_ARCH("armv7-r", cortexr4,	TF_CO_PROC, 7R,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7R))
-ARM_ARCH("armv7-m", cortexm3,	TF_CO_PROC, 7M,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7M))
-ARM_ARCH("armv7e-m", cortexm4,  TF_CO_PROC, 7EM,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7EM))
-ARM_ARCH("armv8-a", cortexa53,  TF_CO_PROC, 8A,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH8A))
-ARM_ARCH("armv8-a+crc",cortexa53, TF_CO_PROC, 8A,   ARM_FSET_MAKE_CPU1 (FL_CRC32  | FL_FOR_ARCH8A))
-ARM_ARCH("armv8.1-a", cortexa53,  TF_CO_PROC, 8A,   ARM_FSET_MAKE (FL_CRC32 | FL_FOR_ARCH8A, FL2_FOR_ARCH8_1A))
-ARM_ARCH("armv8.1-a+crc",cortexa53, TF_CO_PROC, 8A, ARM_FSET_MAKE (FL_CRC32 | FL_FOR_ARCH8A, FL2_FOR_ARCH8_1A))
-ARM_ARCH ("armv8.2-a", cortexa53,  TF_CO_PROC, 8A,  ARM_FSET_MAKE (FL_CRC32 | FL_FOR_ARCH8A, FL2_FOR_ARCH8_2A))
-ARM_ARCH ("armv8.2-a+fp16", cortexa53,  TF_CO_PROC, 8A, ARM_FSET_MAKE (FL_CRC32 | FL_FOR_ARCH8A, FL2_FOR_ARCH8_2A | FL2_FP16INST))
-ARM_ARCH("armv8-m.base", cortexm23, 0,	      8M_BASE, ARM_FSET_MAKE (FL_FOR_ARCH8M_BASE, FL2_CMSE))
-ARM_ARCH("armv8-m.main", cortexm7, TF_CO_PROC, 8M_MAIN, ARM_FSET_MAKE (FL_FOR_ARCH8M_MAIN, FL2_CMSE))
-ARM_ARCH("armv8-m.main+dsp", cortexm33, TF_CO_PROC, 8M_MAIN, ARM_FSET_MAKE (FL_ARCH7EM | FL_FOR_ARCH8M_MAIN, FL2_CMSE))
-ARM_ARCH("iwmmxt",  iwmmxt,     (TF_LDSCHED | TF_STRONG | TF_XSCALE), 5TE,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT))
-ARM_ARCH("iwmmxt2", iwmmxt2,    (TF_LDSCHED | TF_STRONG | TF_XSCALE), 5TE,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2))
+ARM_ARCH("armv4t",  arm7tdmi,   TF_CO_PROC,		     4T,	ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T))
+ARM_ARCH("armv5",   arm10tdmi,  TF_CO_PROC, 		     5,		ISA_FEAT(ISA_ARMv5), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5))
+ARM_ARCH("armv5t",  arm10tdmi,  TF_CO_PROC, 		     5T,	ISA_FEAT(ISA_ARMv5t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5T))
+ARM_ARCH("armv5e",  arm1026ejs, TF_CO_PROC, 		     5E,	ISA_FEAT(ISA_ARMv5e), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5E))
+ARM_ARCH("armv5te", arm1026ejs, TF_CO_PROC, 		     5TE,	ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE))
+ARM_ARCH("armv6",   arm1136js,  TF_CO_PROC, 		     6,		ISA_FEAT(ISA_ARMv6), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6))
+ARM_ARCH("armv6j",  arm1136js,  TF_CO_PROC, 		     6J,	ISA_FEAT(ISA_ARMv6j), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6J))
+ARM_ARCH("armv6k",  mpcore,	TF_CO_PROC, 		     6K,	ISA_FEAT(ISA_ARMv6k), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6K))
+ARM_ARCH("armv6z",  arm1176jzs, TF_CO_PROC, 		     6Z,	ISA_FEAT(ISA_ARMv6z), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6Z))
+ARM_ARCH("armv6kz", arm1176jzs, TF_CO_PROC, 		     6KZ,	ISA_FEAT(ISA_ARMv6kz), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6KZ))
+ARM_ARCH("armv6zk", arm1176jzs, TF_CO_PROC, 		     6KZ,	ISA_FEAT(ISA_ARMv6kz), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6KZ))
+ARM_ARCH("armv6t2", arm1156t2s, TF_CO_PROC, 		     6T2,	ISA_FEAT(ISA_ARMv6t2), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6T2))
+ARM_ARCH("armv6-m", cortexm1,	0,			     6M,	ISA_FEAT(ISA_ARMv6m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M))
+ARM_ARCH("armv6s-m", cortexm1,	0, 			     6M,	ISA_FEAT(ISA_ARMv6m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M))
+ARM_ARCH("armv7",   cortexa8,	TF_CO_PROC,		     7,		ISA_FEAT(ISA_ARMv7), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7))
+ARM_ARCH("armv7-a", cortexa8,	TF_CO_PROC,		     7A,	ISA_FEAT(ISA_ARMv7a), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A))
+ARM_ARCH("armv7ve", cortexa8,	TF_CO_PROC,		     7A,	ISA_FEAT(ISA_ARMv7ve), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7VE))
+ARM_ARCH("armv7-r", cortexr4,	TF_CO_PROC,		     7R,	ISA_FEAT(ISA_ARMv7r), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7R))
+ARM_ARCH("armv7-m", cortexm3,	TF_CO_PROC,		     7M,	ISA_FEAT(ISA_ARMv7m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7M))
+ARM_ARCH("armv7e-m", cortexm4,  TF_CO_PROC,		     7EM,	ISA_FEAT(ISA_ARMv7em), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7EM))
+ARM_ARCH("armv8-a", cortexa53,  TF_CO_PROC,		     8A,	ISA_FEAT(ISA_ARMv8a), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH8A))
+ARM_ARCH("armv8-a+crc",cortexa53, TF_CO_PROC,		     8A,	ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32  | FL_FOR_ARCH8A))
+ARM_ARCH("armv8.1-a", cortexa53,  TF_CO_PROC,		     8A,	ISA_FEAT(ISA_ARMv8_1a), ARM_FSET_MAKE (FL_CRC32 | FL_FOR_ARCH8A, FL2_FOR_ARCH8_1A))
+ARM_ARCH ("armv8.2-a", cortexa53,  TF_CO_PROC,		     8A,	ISA_FEAT(ISA_ARMv8_2a), ARM_FSET_MAKE (FL_CRC32 | FL_FOR_ARCH8A, FL2_FOR_ARCH8_2A))
+ARM_ARCH ("armv8.2-a+fp16", cortexa53, TF_CO_PROC,	     8A,	ISA_FEAT(ISA_ARMv8_2a) ISA_FEAT(isa_bit_fp16), ARM_FSET_MAKE (FL_CRC32 | FL_FOR_ARCH8A, FL2_FOR_ARCH8_2A | FL2_FP16INST))
+ARM_ARCH("armv8-m.base", cortexm23, 0,			     8M_BASE,	ISA_FEAT(ISA_ARMv8m_base), ARM_FSET_MAKE (FL_FOR_ARCH8M_BASE, FL2_CMSE))
+ARM_ARCH("armv8-m.main", cortexm7, TF_CO_PROC,		     8M_MAIN,	ISA_FEAT(ISA_ARMv8m_main), ARM_FSET_MAKE (FL_FOR_ARCH8M_MAIN, FL2_CMSE))
+ARM_ARCH("armv8-m.main+dsp", cortexm33, TF_CO_PROC,	     8M_MAIN,	ISA_FEAT(ISA_ARMv8m_main) ISA_FEAT(isa_bit_ARMv7em), ARM_FSET_MAKE (FL_ARCH7EM | FL_FOR_ARCH8M_MAIN, FL2_CMSE))
+ARM_ARCH("iwmmxt",  iwmmxt, (TF_LDSCHED | TF_STRONG | TF_XSCALE), 5TE,	ISA_FEAT(ISA_ARMv5te) ISA_FEAT(isa_bit_xscale) ISA_FEAT(isa_bit_iwmmxt), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT))
+ARM_ARCH("iwmmxt2", iwmmxt2, (TF_LDSCHED | TF_STRONG | TF_XSCALE), 5TE,	ISA_FEAT(ISA_ARMv5te) ISA_FEAT(isa_bit_xscale) ISA_FEAT(isa_bit_iwmmxt) ISA_FEAT(isa_bit_iwmmxt2), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2))
diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
index 27b156a..7c951f3 100644
--- a/gcc/config/arm/arm-cores.def
+++ b/gcc/config/arm/arm-cores.def
@@ -25,7 +25,7 @@
 
 /* Before using #include to read this file, define a macro:
 
-      ARM_CORE(CORE_NAME, INTERNAL_IDENT, TUNE_IDENT, TUNE_FLAGS, ARCH, FLAGS, COSTS)
+      ARM_CORE(CORE_NAME, INTERNAL_IDENT, TUNE_IDENT, TUNE_FLAGS, ARCH, ISA, FLAGS, COSTS)
 
    The CORE_NAME is the name of the core, represented as a string constant.
    The INTERNAL_IDENT is the name of the core represented as an identifier.
@@ -34,6 +34,7 @@
    should be made, represented as an identifier.
    TUNE_FLAGS is a set of flag bits that are used to affect tuning.
    ARCH is the architecture revision implemented by the chip.
+   ISA is the detailed architectural capabilities of the core (see arm-isa.h).
    FLAGS is the set of feature flags of that core.
    This need not include flags implied by the architecture.
    COSTS is the name of the rtx_costs routine to use.
@@ -44,144 +45,146 @@
    Some tools assume no whitespace up to the first "," in each entry.  */
 
 /* V2/V2A Architecture Processors */
-ARM_CORE("arm2",	arm2, arm2,		(TF_CO_PROC | TF_NO_MODE32), 2,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2), slowmul)
-ARM_CORE("arm250",	arm250, arm250,		(TF_CO_PROC | TF_NO_MODE32), 2,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2), slowmul)
-ARM_CORE("arm3",	arm3, arm3,		(TF_CO_PROC | TF_NO_MODE32), 2,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2), slowmul)
+ARM_CORE("arm2",	arm2, arm2,		(TF_CO_PROC | TF_NO_MODE32),	  2,	ISA_FEAT(ISA_ARMv2) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2), slowmul)
+ARM_CORE("arm250",	arm250, arm250,		(TF_CO_PROC | TF_NO_MODE32), 	  2,	ISA_FEAT(ISA_ARMv2) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2), slowmul)
+ARM_CORE("arm3",	arm3, arm3,		(TF_CO_PROC | TF_NO_MODE32), 	  2,	ISA_FEAT(ISA_ARMv2) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2), slowmul)
 
 /* V3 Architecture Processors */
-ARM_CORE("arm6",	arm6, arm6,		TF_CO_PROC, 3,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm60",	arm60, arm60,		TF_CO_PROC, 3,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm600",	arm600, arm600,		(TF_CO_PROC | TF_WBUF), 3,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm610",	arm610, arm610,		TF_WBUF, 3,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm620",	arm620, arm620,		(TF_CO_PROC | TF_WBUF), 3,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm7",	arm7, arm7,		TF_CO_PROC, 3,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm7d",	arm7d, arm7d,		TF_CO_PROC, 3,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm7di",	arm7di, arm7di,		TF_CO_PROC, 3,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm70",	arm70, arm70,		TF_CO_PROC, 3,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm700",	arm700, arm700,		(TF_CO_PROC | TF_WBUF), 3,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm700i",	arm700i, arm700i,	(TF_CO_PROC | TF_WBUF), 3,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm710",	arm710, arm710,		TF_WBUF, 3,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm720",	arm720, arm720,		TF_WBUF, 3,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm710c",	arm710c, arm710c,	TF_WBUF, 3,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm7100",	arm7100, arm7100,	TF_WBUF, 3,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm7500",	arm7500, arm7500,	TF_WBUF, 3,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-/* Doesn't have an external co-proc, but does have embedded fpa. */
-ARM_CORE("arm7500fe", arm7500fe, arm7500fe,	(TF_CO_PROC | TF_WBUF), 3,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm6",	arm6, arm6,		TF_CO_PROC,			  3,	ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm60",	arm60, arm60,		TF_CO_PROC, 		     	  3,   	ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm600",	arm600, arm600,		(TF_CO_PROC | TF_WBUF),      	  3,	ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm610",	arm610, arm610,		TF_WBUF,      		     	  3,	ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm620",	arm620, arm620,		(TF_CO_PROC | TF_WBUF),      	  3,	ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm7",	arm7, arm7,		TF_CO_PROC,   		     	  3,	ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm7d",	arm7d, arm7d,		TF_CO_PROC, 		     	  3,	ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm7di",	arm7di, arm7di,		TF_CO_PROC, 		     	  3,	ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm70",	arm70, arm70,		TF_CO_PROC, 		     	  3,	ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm700",	arm700, arm700,		(TF_CO_PROC | TF_WBUF),      	  3,	ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm700i",	arm700i, arm700i,	(TF_CO_PROC | TF_WBUF),      	  3,	ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm710",	arm710, arm710,		TF_WBUF,      		     	  3,	ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm720",	arm720, arm720,		TF_WBUF, 		     	  3,	ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm710c",	arm710c, arm710c,	TF_WBUF, 		     	  3,	ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm7100",	arm7100, arm7100,	TF_WBUF, 		     	  3,	ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm7500",	arm7500, arm7500,	TF_WBUF, 		     	  3,	ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+/* Doesn't have an external co-proc, but does have embedded fpa (fpa no-longer supported). */
+ARM_CORE("arm7500fe", arm7500fe, arm7500fe,	(TF_CO_PROC | TF_WBUF),		  3,	ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
 
 /* V3M Architecture Processors */
 /* arm7m doesn't exist on its own, but only with D, ("and", and I), but
    those don't alter the code, so arm7m is sometimes used.  */
-ARM_CORE("arm7m",   arm7m, arm7m,		TF_CO_PROC, 3M,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3M), fastmul)
-ARM_CORE("arm7dm",  arm7dm, arm7dm,		TF_CO_PROC, 3M,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3M), fastmul)
-ARM_CORE("arm7dmi", arm7dmi, arm7dmi,		TF_CO_PROC, 3M,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3M), fastmul)
+ARM_CORE("arm7m",   arm7m, arm7m,		TF_CO_PROC,			  3M,	ISA_FEAT(ISA_ARMv3m) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3M), fastmul)
+ARM_CORE("arm7dm",  arm7dm, arm7dm,		TF_CO_PROC, 		     	  3M,	ISA_FEAT(ISA_ARMv3m) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3M), fastmul)
+ARM_CORE("arm7dmi", arm7dmi, arm7dmi,		TF_CO_PROC, 		     	  3M,	ISA_FEAT(ISA_ARMv3m) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3M), fastmul)
 
 /* V4 Architecture Processors */
-ARM_CORE("arm8",          arm8, arm8,			TF_LDSCHED, 4,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), fastmul)
-ARM_CORE("arm810",        arm810, arm810,		TF_LDSCHED, 4,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), fastmul)
-ARM_CORE("strongarm",     strongarm, strongarm,		(TF_LDSCHED | TF_STRONG), 4,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), strongarm)
-ARM_CORE("strongarm110",  strongarm110, strongarm110,	(TF_LDSCHED | TF_STRONG), 4,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), strongarm)
-ARM_CORE("strongarm1100", strongarm1100, strongarm1100, (TF_LDSCHED | TF_STRONG), 4,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), strongarm)
-ARM_CORE("strongarm1110", strongarm1110, strongarm1110, (TF_LDSCHED | TF_STRONG), 4,	ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), strongarm)
-ARM_CORE("fa526",         fa526, fa526,			TF_LDSCHED, 4,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4), fastmul)
-ARM_CORE("fa626",         fa626, fa626,			TF_LDSCHED, 4,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4), fastmul)
+ARM_CORE("arm8",          arm8, arm8,			TF_LDSCHED,		  4,	ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), fastmul)
+ARM_CORE("arm810",        arm810, arm810,		TF_LDSCHED, 		  4,	ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), fastmul)
+ARM_CORE("strongarm",     strongarm, strongarm,		(TF_LDSCHED | TF_STRONG), 4,	ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), strongarm)
+ARM_CORE("strongarm110",  strongarm110, strongarm110,	(TF_LDSCHED | TF_STRONG), 4,	ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), strongarm)
+ARM_CORE("strongarm1100", strongarm1100, strongarm1100, (TF_LDSCHED | TF_STRONG), 4,	ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), strongarm)
+ARM_CORE("strongarm1110", strongarm1110, strongarm1110, (TF_LDSCHED | TF_STRONG), 4,	ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), strongarm)
+ARM_CORE("fa526",         fa526, fa526,			TF_LDSCHED,   		  4,	ISA_FEAT(ISA_ARMv4), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4), fastmul)
+ARM_CORE("fa626",         fa626, fa626,			TF_LDSCHED, 		  4,	ISA_FEAT(ISA_ARMv4), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4), fastmul)
 
 /* V4T Architecture Processors */
-ARM_CORE("arm7tdmi",	arm7tdmi, arm7tdmi,	TF_CO_PROC, 4T,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm7tdmi-s",	arm7tdmis, arm7tdmis,	TF_CO_PROC, 4T,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm710t",	arm710t, arm710t,	TF_WBUF, 4T,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T),    fastmul)
-ARM_CORE("arm720t",	arm720t, arm720t,	TF_WBUF, 4T,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T),    fastmul)
-ARM_CORE("arm740t",	arm740t, arm740t,	TF_WBUF, 4T,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T),    fastmul)
-ARM_CORE("arm9",	arm9, arm9,		TF_LDSCHED, 4T,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm9tdmi",	arm9tdmi, arm9tdmi,	TF_LDSCHED, 4T,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm920",	arm920, arm920,		TF_LDSCHED, 4T,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm920t",	arm920t, arm920t,	TF_LDSCHED, 4T,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm922t",	arm922t, arm922t,	TF_LDSCHED, 4T,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm940t",	arm940t, arm940t,	TF_LDSCHED, 4T,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
-ARM_CORE("ep9312",	ep9312, ep9312,		TF_LDSCHED, 4T,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm7tdmi",	arm7tdmi, arm7tdmi,	TF_CO_PROC,			  4T,	ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm7tdmi-s",	arm7tdmis, arm7tdmis,	TF_CO_PROC, 			  4T,	ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm710t",	arm710t, arm710t,	TF_WBUF, 			  4T,	ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm720t",	arm720t, arm720t,	TF_WBUF, 			  4T,	ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm740t",	arm740t, arm740t,	TF_WBUF, 			  4T,	ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm9",	arm9, arm9,		TF_LDSCHED, 			  4T,	ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm9tdmi",	arm9tdmi, arm9tdmi,	TF_LDSCHED, 			  4T,	ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm920",	arm920, arm920,		TF_LDSCHED, 			  4T,	ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm920t",	arm920t, arm920t,	TF_LDSCHED, 			  4T,	ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm922t",	arm922t, arm922t,	TF_LDSCHED, 			  4T,	ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm940t",	arm940t, arm940t,	TF_LDSCHED, 			  4T,	ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
+ARM_CORE("ep9312",	ep9312, ep9312,		TF_LDSCHED, 			  4T,	ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
 
 /* V5T Architecture Processors */
-ARM_CORE("arm10tdmi",	arm10tdmi, arm10tdmi,	TF_LDSCHED, 5T,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5T), fastmul)
-ARM_CORE("arm1020t",	arm1020t, arm1020t,	TF_LDSCHED, 5T,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5T), fastmul)
+ARM_CORE("arm10tdmi",	arm10tdmi, arm10tdmi,	TF_LDSCHED,			  5T,	ISA_FEAT(ISA_ARMv5t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5T), fastmul)
+ARM_CORE("arm1020t",	arm1020t, arm1020t,	TF_LDSCHED, 			  5T,	ISA_FEAT(ISA_ARMv5t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5T), fastmul)
 
 /* V5TE Architecture Processors */
-ARM_CORE("arm9e",	arm9e, arm9e,		TF_LDSCHED, 5TE,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
-ARM_CORE("arm946e-s",	arm946es, arm946es,	TF_LDSCHED, 5TE,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
-ARM_CORE("arm966e-s",	arm966es, arm966es,	TF_LDSCHED, 5TE,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
-ARM_CORE("arm968e-s",	arm968es, arm968es,	TF_LDSCHED, 5TE,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
-ARM_CORE("arm10e",	arm10e, arm10e,		TF_LDSCHED, 5TE,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), fastmul)
-ARM_CORE("arm1020e",	arm1020e, arm1020e,	TF_LDSCHED, 5TE,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), fastmul)
-ARM_CORE("arm1022e",	arm1022e, arm1022e,	TF_LDSCHED, 5TE,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), fastmul)
-ARM_CORE("xscale",	xscale, xscale,		(TF_LDSCHED | TF_XSCALE), 5TE,	ARM_FSET_MAKE_CPU1 (FL_XSCALE | FL_FOR_ARCH5TE), xscale)
-ARM_CORE("iwmmxt",	iwmmxt, iwmmxt,		(TF_LDSCHED | TF_XSCALE), 5TE,	ARM_FSET_MAKE_CPU1 (FL_XSCALE | FL_IWMMXT | FL_FOR_ARCH5TE), xscale)
-ARM_CORE("iwmmxt2",	iwmmxt2, iwmmxt2,	(TF_LDSCHED | TF_XSCALE), 5TE,	ARM_FSET_MAKE_CPU1 (FL_XSCALE | FL_IWMMXT | FL_IWMMXT2 | FL_FOR_ARCH5TE), xscale)
-ARM_CORE("fa606te",	fa606te, fa606te,	TF_LDSCHED, 5TE,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
-ARM_CORE("fa626te",	fa626te, fa626te,	TF_LDSCHED, 5TE,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
-ARM_CORE("fmp626",	fmp626, fmp626,		TF_LDSCHED, 5TE,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
-ARM_CORE("fa726te",	fa726te, fa726te,	TF_LDSCHED, 5TE,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), fa726te)
+ARM_CORE("arm9e",	arm9e, arm9e,		TF_LDSCHED,			  5TE,	ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
+ARM_CORE("arm946e-s",	arm946es, arm946es,	TF_LDSCHED, 			  5TE,	ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
+ARM_CORE("arm966e-s",	arm966es, arm966es,	TF_LDSCHED, 			  5TE,	ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
+ARM_CORE("arm968e-s",	arm968es, arm968es,	TF_LDSCHED, 			  5TE,	ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
+ARM_CORE("arm10e",	arm10e, arm10e,		TF_LDSCHED, 			  5TE,	ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), fastmul)
+ARM_CORE("arm1020e",	arm1020e, arm1020e,	TF_LDSCHED, 			  5TE,	ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), fastmul)
+ARM_CORE("arm1022e",	arm1022e, arm1022e,	TF_LDSCHED, 			  5TE,	ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), fastmul)
+ARM_CORE("xscale",	xscale, xscale,		(TF_LDSCHED | TF_XSCALE), 	  5TE,	ISA_FEAT(ISA_ARMv5te) ISA_FEAT(isa_bit_xscale), ARM_FSET_MAKE_CPU1 (FL_XSCALE | FL_FOR_ARCH5TE), xscale)
+ARM_CORE("iwmmxt",	iwmmxt, iwmmxt,		(TF_LDSCHED | TF_XSCALE), 	  5TE,	ISA_FEAT(ISA_ARMv5te) ISA_FEAT(isa_bit_xscale) ISA_FEAT(isa_bit_iwmmxt), ARM_FSET_MAKE_CPU1 (FL_XSCALE | FL_IWMMXT | FL_FOR_ARCH5TE), xscale)
+ARM_CORE("iwmmxt2",	iwmmxt2, iwmmxt2,	(TF_LDSCHED | TF_XSCALE), 	  5TE,	ISA_FEAT(ISA_ARMv5te) ISA_FEAT(isa_bit_xscale) ISA_FEAT(isa_bit_iwmmxt) ISA_FEAT(isa_bit_iwmmxt2), ARM_FSET_MAKE_CPU1 (FL_XSCALE | FL_IWMMXT | FL_IWMMXT2 | FL_FOR_ARCH5TE), xscale)
+ARM_CORE("fa606te",	fa606te, fa606te,	TF_LDSCHED,   			  5TE,	ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
+ARM_CORE("fa626te",	fa626te, fa626te,	TF_LDSCHED, 			  5TE,	ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
+ARM_CORE("fmp626",	fmp626, fmp626,		TF_LDSCHED, 			  5TE,	ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
+ARM_CORE("fa726te",	fa726te, fa726te,	TF_LDSCHED, 			  5TE,	ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), fa726te)
 
 /* V5TEJ Architecture Processors */
-ARM_CORE("arm926ej-s",	arm926ejs, arm926ejs,	TF_LDSCHED, 5TEJ,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TEJ), 9e)
-ARM_CORE("arm1026ej-s",	arm1026ejs, arm1026ejs,	TF_LDSCHED, 5TEJ,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TEJ), 9e)
+ARM_CORE("arm926ej-s",	arm926ejs, arm926ejs,	TF_LDSCHED,			  5TEJ,	ISA_FEAT(ISA_ARMv5tej), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TEJ), 9e)
+ARM_CORE("arm1026ej-s",	arm1026ejs, arm1026ejs,	TF_LDSCHED, 			  5TEJ,	ISA_FEAT(ISA_ARMv5tej), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TEJ), 9e)
 
 /* V6 Architecture Processors */
-ARM_CORE("arm1136j-s",		arm1136js, arm1136js,		TF_LDSCHED, 6J,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6J), 9e)
-ARM_CORE("arm1136jf-s",		arm1136jfs, arm1136jfs,		TF_LDSCHED, 6J,	ARM_FSET_MAKE_CPU1 (FL_VFPV2 | FL_FOR_ARCH6J), 9e)
-ARM_CORE("arm1176jz-s",		arm1176jzs, arm1176jzs,		TF_LDSCHED, 6KZ,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6KZ), 9e)
-ARM_CORE("arm1176jzf-s",	arm1176jzfs, arm1176jzfs,	TF_LDSCHED, 6KZ,	ARM_FSET_MAKE_CPU1 (FL_VFPV2 | FL_FOR_ARCH6KZ), 9e)
-ARM_CORE("mpcorenovfp",		mpcorenovfp, mpcorenovfp,	TF_LDSCHED, 6K,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6K), 9e)
-ARM_CORE("mpcore",		mpcore, mpcore,			TF_LDSCHED, 6K,	ARM_FSET_MAKE_CPU1 (FL_VFPV2 | FL_FOR_ARCH6K), 9e)
-ARM_CORE("arm1156t2-s",		arm1156t2s, arm1156t2s,		TF_LDSCHED, 6T2,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6T2), v6t2)
-ARM_CORE("arm1156t2f-s",	arm1156t2fs, arm1156t2fs,	TF_LDSCHED, 6T2,	ARM_FSET_MAKE_CPU1 (FL_VFPV2 | FL_FOR_ARCH6T2), v6t2)
+ARM_CORE("arm1136j-s",		arm1136js, arm1136js,		TF_LDSCHED,	  6J,	ISA_FEAT(ISA_ARMv6j), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6J), 9e)
+ARM_CORE("arm1136jf-s",		arm1136jfs, arm1136jfs,		TF_LDSCHED, 	  6J,	ISA_FEAT(ISA_ARMv6j) ISA_FEAT(isa_bit_VFPv2), ARM_FSET_MAKE_CPU1 (FL_VFPV2 | FL_FOR_ARCH6J), 9e)
+ARM_CORE("arm1176jz-s",		arm1176jzs, arm1176jzs,		TF_LDSCHED, 	  6KZ,	ISA_FEAT(ISA_ARMv6kz), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6KZ), 9e)
+ARM_CORE("arm1176jzf-s",	arm1176jzfs, arm1176jzfs,	TF_LDSCHED, 	  6KZ,	ISA_FEAT(ISA_ARMv6kz) ISA_FEAT(isa_bit_VFPv2), ARM_FSET_MAKE_CPU1 (FL_VFPV2 | FL_FOR_ARCH6KZ), 9e)
+ARM_CORE("mpcorenovfp",		mpcorenovfp, mpcorenovfp,	TF_LDSCHED, 	  6K,	ISA_FEAT(ISA_ARMv6k), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6K), 9e)
+ARM_CORE("mpcore",		mpcore, mpcore,			TF_LDSCHED, 	  6K,	ISA_FEAT(ISA_ARMv6k) ISA_FEAT(isa_bit_VFPv2), ARM_FSET_MAKE_CPU1 (FL_VFPV2 | FL_FOR_ARCH6K), 9e)
+ARM_CORE("arm1156t2-s",		arm1156t2s, arm1156t2s,		TF_LDSCHED, 	  6T2,	ISA_FEAT(ISA_ARMv6t2), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6T2), v6t2)
+ARM_CORE("arm1156t2f-s",	arm1156t2fs, arm1156t2fs,	TF_LDSCHED, 	  6T2,	ISA_FEAT(ISA_ARMv6t2) ISA_FEAT(isa_bit_VFPv2), ARM_FSET_MAKE_CPU1 (FL_VFPV2 | FL_FOR_ARCH6T2), v6t2)
 
 /* V6M Architecture Processors */
-ARM_CORE("cortex-m1",		cortexm1, cortexm1,		TF_LDSCHED, 6M,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
-ARM_CORE("cortex-m0",		cortexm0, cortexm0,		TF_LDSCHED, 6M,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
-ARM_CORE("cortex-m0plus",	cortexm0plus, cortexm0plus,	TF_LDSCHED, 6M,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
+ARM_CORE("cortex-m1",		cortexm1, cortexm1,		TF_LDSCHED,	  6M,	ISA_FEAT(ISA_ARMv6m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
+ARM_CORE("cortex-m0",		cortexm0, cortexm0,		TF_LDSCHED, 	  6M,	ISA_FEAT(ISA_ARMv6m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
+ARM_CORE("cortex-m0plus",	cortexm0plus, cortexm0plus,	TF_LDSCHED, 	  6M,	ISA_FEAT(ISA_ARMv6m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
 
 /* V6M Architecture Processors for small-multiply implementations.  */
-ARM_CORE("cortex-m1.small-multiply",	cortexm1smallmultiply, cortexm1,	(TF_LDSCHED | TF_SMALLMUL), 6M,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
-ARM_CORE("cortex-m0.small-multiply",	cortexm0smallmultiply, cortexm0,	(TF_LDSCHED | TF_SMALLMUL), 6M,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
-ARM_CORE("cortex-m0plus.small-multiply",cortexm0plussmallmultiply, cortexm0plus, (TF_LDSCHED | TF_SMALLMUL), 6M,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
+ARM_CORE("cortex-m1.small-multiply",	cortexm1smallmultiply, cortexm1,	(TF_LDSCHED | TF_SMALLMUL),  6M,	ISA_FEAT(ISA_ARMv6m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
+ARM_CORE("cortex-m0.small-multiply",	cortexm0smallmultiply, cortexm0,	(TF_LDSCHED | TF_SMALLMUL),  6M,	ISA_FEAT(ISA_ARMv6m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
+ARM_CORE("cortex-m0plus.small-multiply",cortexm0plussmallmultiply, cortexm0plus, (TF_LDSCHED | TF_SMALLMUL), 6M,	ISA_FEAT(ISA_ARMv6m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
 
 /* V7 Architecture Processors */
-ARM_CORE("generic-armv7-a",	genericv7a, genericv7a,		TF_LDSCHED, 7A,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), cortex)
-ARM_CORE("cortex-a5",		cortexa5, cortexa5,		TF_LDSCHED, 7A,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), cortex_a5)
-ARM_CORE("cortex-a7",		cortexa7, cortexa7,		TF_LDSCHED, 7A,	ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a7)
-ARM_CORE("cortex-a8",		cortexa8, cortexa8,		TF_LDSCHED, 7A,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), cortex_a8)
-ARM_CORE("cortex-a9",		cortexa9, cortexa9,		TF_LDSCHED, 7A,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), cortex_a9)
-ARM_CORE("cortex-a12",		cortexa12, cortexa17,		TF_LDSCHED, 7A,	ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12)
-ARM_CORE("cortex-a15",		cortexa15, cortexa15,		TF_LDSCHED, 7A,	ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a15)
-ARM_CORE("cortex-a17",		cortexa17, cortexa17,		TF_LDSCHED, 7A,	ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12)
-ARM_CORE("cortex-r4",		cortexr4, cortexr4,		TF_LDSCHED, 7R,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7R), cortex)
-ARM_CORE("cortex-r4f",		cortexr4f, cortexr4f,		TF_LDSCHED, 7R,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7R), cortex)
-ARM_CORE("cortex-r5",		cortexr5, cortexr5,		TF_LDSCHED, 7R,	ARM_FSET_MAKE_CPU1 (FL_ARM_DIV | FL_FOR_ARCH7R), cortex)
-ARM_CORE("cortex-r7",		cortexr7, cortexr7,		TF_LDSCHED, 7R,	ARM_FSET_MAKE_CPU1 (FL_ARM_DIV | FL_FOR_ARCH7R), cortex)
-ARM_CORE("cortex-r8",		cortexr8, cortexr7,		TF_LDSCHED, 7R,	ARM_FSET_MAKE_CPU1 (FL_ARM_DIV | FL_FOR_ARCH7R), cortex)
-ARM_CORE("cortex-m7",		cortexm7, cortexm7,		TF_LDSCHED, 7EM,	ARM_FSET_MAKE_CPU1 (FL_NO_VOLATILE_CE | FL_FOR_ARCH7EM), cortex_m7)
-ARM_CORE("cortex-m4",		cortexm4, cortexm4,		TF_LDSCHED, 7EM,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7EM), v7m)
-ARM_CORE("cortex-m3",		cortexm3, cortexm3,		TF_LDSCHED, 7M,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7M), v7m)
-ARM_CORE("marvell-pj4",		marvell_pj4, marvell_pj4,	TF_LDSCHED, 7A,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), marvell_pj4)
+ARM_CORE("generic-armv7-a",	genericv7a, genericv7a,		TF_LDSCHED,	  7A,	ISA_FEAT(ISA_ARMv7a), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), cortex)
+ARM_CORE("cortex-a5",		cortexa5, cortexa5,		TF_LDSCHED, 	  7A,	ISA_FEAT(ISA_ARMv7a), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), cortex_a5)
+ARM_CORE("cortex-a7",		cortexa7, cortexa7,		TF_LDSCHED, 	  7A,	ISA_FEAT(ISA_ARMv7a) ISA_FEAT(isa_bit_adiv) ISA_FEAT(isa_bit_tdiv), ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a7)
+ARM_CORE("cortex-a8",		cortexa8, cortexa8,		TF_LDSCHED, 	  7A,	ISA_FEAT(ISA_ARMv7a), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), cortex_a8)
+ARM_CORE("cortex-a9",		cortexa9, cortexa9,		TF_LDSCHED, 	  7A,	ISA_FEAT(ISA_ARMv7a), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), cortex_a9)
+ARM_CORE("cortex-a12",		cortexa12, cortexa17,		TF_LDSCHED, 	  7A,	ISA_FEAT(ISA_ARMv7a) ISA_FEAT(isa_bit_adiv) ISA_FEAT(isa_bit_tdiv), ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12)
+ARM_CORE("cortex-a15",		cortexa15, cortexa15,		TF_LDSCHED, 	  7A,	ISA_FEAT(ISA_ARMv7ve), ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a15)
+ARM_CORE("cortex-a17",		cortexa17, cortexa17,		TF_LDSCHED, 	  7A,	ISA_FEAT(ISA_ARMv7ve), ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12)
+ARM_CORE("cortex-r4",		cortexr4, cortexr4,		TF_LDSCHED, 	  7R,	ISA_FEAT(ISA_ARMv7r), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7R), cortex)
+ARM_CORE("cortex-r4f",		cortexr4f, cortexr4f,		TF_LDSCHED, 	  7R,	ISA_FEAT(ISA_ARMv7r), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7R), cortex)
+ARM_CORE("cortex-r5",		cortexr5, cortexr5,		TF_LDSCHED, 	  7R,	ISA_FEAT(ISA_ARMv7r) ISA_FEAT(isa_bit_adiv), ARM_FSET_MAKE_CPU1 (FL_ARM_DIV | FL_FOR_ARCH7R), cortex)
+ARM_CORE("cortex-r7",		cortexr7, cortexr7,		TF_LDSCHED, 	  7R,	ISA_FEAT(ISA_ARMv7r) ISA_FEAT(isa_bit_adiv), ARM_FSET_MAKE_CPU1 (FL_ARM_DIV | FL_FOR_ARCH7R), cortex)
+ARM_CORE("cortex-r8",		cortexr8, cortexr7,		TF_LDSCHED, 	  7R,	ISA_FEAT(ISA_ARMv7r) ISA_FEAT(isa_bit_adiv), ARM_FSET_MAKE_CPU1 (FL_ARM_DIV | FL_FOR_ARCH7R), cortex)
+ARM_CORE("cortex-m7",		cortexm7, cortexm7,		TF_LDSCHED, 	  7EM,	ISA_FEAT(ISA_ARMv7em) ISA_FEAT(isa_quirk_no_volatile_ce), ARM_FSET_MAKE_CPU1 (FL_NO_VOLATILE_CE | FL_FOR_ARCH7EM), cortex_m7)
+ARM_CORE("cortex-m4",		cortexm4, cortexm4,		TF_LDSCHED, 	  7EM,	ISA_FEAT(ISA_ARMv7em), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7EM), v7m)
+ARM_CORE("cortex-m3",		cortexm3, cortexm3,		TF_LDSCHED, 	  7M,	ISA_FEAT(ISA_ARMv7m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7M), v7m)
+ARM_CORE("marvell-pj4",		marvell_pj4, marvell_pj4,	TF_LDSCHED, 	  7A,	ISA_FEAT(ISA_ARMv7a), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), marvell_pj4)
 
 /* V7 big.LITTLE implementations */
-ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7,	TF_LDSCHED, 7A,	ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a15)
-ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7,	TF_LDSCHED, 7A,	ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12)
-
-/* V8 Architecture Processors */
-ARM_CORE("cortex-a32",	cortexa32, cortexa53,	TF_LDSCHED, 8A,	ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a35)
-ARM_CORE("cortex-a35",	cortexa35, cortexa53,	TF_LDSCHED, 8A,	ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a35)
-ARM_CORE("cortex-a53",	cortexa53, cortexa53,	TF_LDSCHED, 8A,	ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a53)
-ARM_CORE("cortex-a57",	cortexa57, cortexa57,	TF_LDSCHED, 8A,	ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
-ARM_CORE("cortex-a72",	cortexa72, cortexa57,	TF_LDSCHED, 8A,	ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
-ARM_CORE("cortex-a73",	cortexa73, cortexa57,	TF_LDSCHED, 8A,	ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a73)
-ARM_CORE("cortex-m23",	cortexm23, cortexm23,	TF_LDSCHED, 8M_BASE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH8M_BASE), v6m)
-ARM_CORE("cortex-m33",	cortexm33, cortexm33,	TF_LDSCHED, 8M_MAIN, ARM_FSET_MAKE_CPU1 (FL_ARCH7EM | FL_FOR_ARCH8M_MAIN), v7m)
-ARM_CORE("exynos-m1",	exynosm1,  exynosm1,	TF_LDSCHED, 8A,	ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), exynosm1)
-ARM_CORE("falkor",	falkor,    cortexa57,	TF_LDSCHED, 8A,	ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), qdf24xx)
-ARM_CORE("qdf24xx",	qdf24xx,   cortexa57,	TF_LDSCHED, 8A,	ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), qdf24xx)
-ARM_CORE("xgene1",      xgene1,    xgene1,      TF_LDSCHED, 8A,	ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH8A),            xgene1)
-
-/* V8 big.LITTLE implementations */
-ARM_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, TF_LDSCHED, 8A,	ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
-ARM_CORE("cortex-a72.cortex-a53", cortexa72cortexa53, cortexa53, TF_LDSCHED, 8A,	ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
-ARM_CORE("cortex-a73.cortex-a35", cortexa73cortexa35, cortexa53, TF_LDSCHED, 8A,	ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a73)
-ARM_CORE("cortex-a73.cortex-a53", cortexa73cortexa53, cortexa53, TF_LDSCHED, 8A,	ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a73)
+ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7,	TF_LDSCHED,	  7A,	ISA_FEAT(ISA_ARMv7ve), ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a15)
+ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7,	TF_LDSCHED, 	  7A,	ISA_FEAT(ISA_ARMv7ve), ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12)
+
+/* V8 A-profile Architecture Processors */
+ARM_CORE("cortex-a32",	cortexa32, cortexa53,	TF_LDSCHED, 			  8A,	ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a35)
+ARM_CORE("cortex-a35",	cortexa35, cortexa53,	TF_LDSCHED, 			  8A,	ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a35)
+ARM_CORE("cortex-a53",	cortexa53, cortexa53,	TF_LDSCHED, 			  8A,	ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a53)
+ARM_CORE("cortex-a57",	cortexa57, cortexa57,	TF_LDSCHED, 			  8A,	ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
+ARM_CORE("cortex-a72",	cortexa72, cortexa57,	TF_LDSCHED, 			  8A,	ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
+ARM_CORE("cortex-a73",	cortexa73, cortexa57,	TF_LDSCHED, 			  8A,	ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a73)
+ARM_CORE("exynos-m1",	exynosm1,  exynosm1,	TF_LDSCHED, 			  8A,	ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), exynosm1)
+ARM_CORE("falkor",	falkor,    cortexa57,	TF_LDSCHED, 			  8A,	ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), qdf24xx)
+ARM_CORE("qdf24xx",	qdf24xx,   cortexa57,	TF_LDSCHED, 			  8A,	ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), qdf24xx)
+ARM_CORE("xgene1",      xgene1,    xgene1,      TF_LDSCHED, 			  8A,	ISA_FEAT(ISA_ARMv8a), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH8A),            xgene1)
+
+/* V8 A-profile big.LITTLE implementations */
+ARM_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, TF_LDSCHED,	  8A,	ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
+ARM_CORE("cortex-a72.cortex-a53", cortexa72cortexa53, cortexa53, TF_LDSCHED, 	  8A,	ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
+ARM_CORE("cortex-a73.cortex-a35", cortexa73cortexa35, cortexa53, TF_LDSCHED, 	  8A,	ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a73)
+ARM_CORE("cortex-a73.cortex-a53", cortexa73cortexa53, cortexa53, TF_LDSCHED, 	  8A,	ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a73)
+
+/* V8 M-profile implementations.  */
+ARM_CORE("cortex-m23",	cortexm23, cortexm23,	TF_LDSCHED,			  8M_BASE, ISA_FEAT(ISA_ARMv8m_base), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH8M_BASE), v6m)
+ARM_CORE("cortex-m33",	cortexm33, cortexm33,	TF_LDSCHED, 			  8M_MAIN, ISA_FEAT(ISA_ARMv8m_main) ISA_FEAT(isa_bit_ARMv7em), ARM_FSET_MAKE_CPU1 (FL_ARCH7EM | FL_FOR_ARCH8M_MAIN), v7m)
diff --git a/gcc/config/arm/arm-isa.h b/gcc/config/arm/arm-isa.h
new file mode 100644
index 0000000..15eb6e1
--- /dev/null
+++ b/gcc/config/arm/arm-isa.h
@@ -0,0 +1,127 @@
+/* ISA feature bits for ARM.
+   Copyright (C) 2016 Free Software Foundation, Inc.
+   Contributed by ARM Ltd.
+
+   This file is part of GCC.
+
+   GCC is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published
+   by the Free Software Foundation; either version 3, or (at your
+   option) any later version.
+
+   GCC is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+#ifndef ARM_ISA_FEATURE_H
+#define ARM_ISA_FEATURE_H
+
+enum isa_feature
+  {
+    isa_nobit,		/* Must be first.  */
+    isa_bit_ARMv3m,	/* Extended multiply.  */
+    isa_bit_mode26,	/* 26-bit mode support.  */
+    isa_bit_mode32,	/* 32-bit mode support.  */
+    isa_bit_ARMv4,	/* Architecture rel 4.  */
+    isa_bit_ARMv5,	/* Architecture rel 5.	*/
+    isa_bit_thumb,	/* Thumb aware.  */
+    isa_bit_ARMv5e,	/* Architecture rel 5e.  */
+    isa_bit_xscale,	/* XScale.  */
+    isa_bit_ARMv6,	/* Architecture rel 6.  */
+    isa_bit_ARMv6k,	/* Architecture rel 6k.  */
+    isa_bit_thumb2,	/* Thumb-2.  */
+    isa_bit_notm,	/* Instructions that are not present in 'M' profile.  */
+    isa_bit_tdiv,	/* Thumb division instructions.  */
+    isa_bit_ARMv7em,	/* Architecture rel 7e-m.  */
+    isa_bit_ARMv7,	/* Architecture rel 7.  */
+    isa_bit_adiv,	/* ARM division instructions.  */
+    isa_bit_ARMv8,	/* Architecture rel 8.  */
+    isa_bit_crc32,	/* ARMv8 CRC32 instructions.  */
+    isa_bit_iwmmxt,	/* XScale v2 (Wireless MMX).  */
+    isa_bit_iwmmxt2,	/* XScale Wireless MMX2.  */
+    isa_bit_ARMv8_1,	/* Architecture rel 8.1.  */
+    isa_bit_ARMv8_2,	/* Architecutre rel 8.2.  */
+    isa_bit_cmse,	/* M-Profile security extensions.  */
+    /* Floating point and Neon extensions.  */
+    isa_bit_VFPv2,	/* Vector floating point v2 (our base level).  */
+    isa_bit_VFPv3,	/* Vector floating point v3.  */
+    isa_bit_neon,	/* Advanced SIMD instructions.  */
+    isa_bit_fp16,	/* FP16 extension (half-precision float).  */
+
+    /* ISA Quirks (errata?).  */
+    isa_quirk_no_volatile_ce,	/* No volatile memory in IT blocks.  */
+    isa_quirk_ARMv6kz,		/* Previously mis-identified by GCC.  */
+
+    /* Aren't currently, but probably should be tuning bits.  */
+    isa_bit_smallmul,	/* Slow multiply operations.  */
+
+    /* Tuning bits.  Should be elsewhere.  */
+    isa_tune_co_proc,	/* Has co-processor bus.  */
+    isa_tune_ldsched,	/* Load scheduling necessary.  */
+    isa_tune_strong,	/* StrongARM.  */
+    isa_tune_wbuf,	/* Schedule for write buffer ops (ARM6 & 7 only).  */
+
+    /* Must be last, used to dimension arrays.  */
+    isa_num_bits
+  };
+
+/* Helper macros for use when defining CPUs and architectures.
+
+   There must be no parenthesees in these lists, since they are used
+   to initialize arrays.  */
+
+#define ISA_ARMv2	isa_bit_notm
+#define ISA_ARMv3	ISA_ARMv2, isa_bit_mode32
+#define ISA_ARMv3m	ISA_ARMv3, isa_bit_ARMv3m
+#define ISA_ARMv4	ISA_ARMv3m, isa_bit_ARMv4
+#define ISA_ARMv4t	ISA_ARMv4, isa_bit_thumb
+#define ISA_ARMv5	ISA_ARMv4, isa_bit_ARMv5
+#define ISA_ARMv5t	ISA_ARMv5, isa_bit_thumb
+#define ISA_ARMv5e	ISA_ARMv5, isa_bit_ARMv5e
+#define ISA_ARMv5te	ISA_ARMv5e, isa_bit_thumb
+#define ISA_ARMv5tej	ISA_ARMv5te
+#define ISA_ARMv6	ISA_ARMv5te, isa_bit_ARMv6
+#define ISA_ARMv6j	ISA_ARMv6
+#define ISA_ARMv6k	ISA_ARMv6, isa_bit_ARMv6k
+#define ISA_ARMv6z	ISA_ARMv6
+#define ISA_ARMv6kz	ISA_ARMv6k, isa_quirk_ARMv6kz
+#define ISA_ARMv6zk	ISA_ARMv6k
+#define ISA_ARMv6t2	ISA_ARMv6, isa_bit_thumb2
+
+/* This is suspect.  ARMv6-m doesn't really pull in any useful features
+   from ARMv5* or ARMv6.  */
+#define ISA_ARMv6m	isa_bit_mode32, isa_bit_ARMv3m, isa_bit_ARMv4, \
+    isa_bit_thumb, isa_bit_ARMv5, isa_bit_ARMv5e, isa_bit_ARMv6
+/* This is suspect, the 'common' ARMv7 subset excludes the thumb2 'DSP' and
+   integer SIMD instructions that are in ARMv6T2.  */
+#define ISA_ARMv7	ISA_ARMv6m, isa_bit_thumb2, isa_bit_ARMv7
+#define ISA_ARMv7a	ISA_ARMv7, isa_bit_notm, isa_bit_ARMv6k
+#define ISA_ARMv7ve	ISA_ARMv7a, isa_bit_adiv, isa_bit_tdiv
+#define ISA_ARMv7r	ISA_ARMv7a, isa_bit_tdiv
+#define ISA_ARMv7m	ISA_ARMv7, isa_bit_tdiv
+#define ISA_ARMv7em	ISA_ARMv7m, isa_bit_ARMv7em
+#define ISA_ARMv8a	ISA_ARMv7ve, isa_bit_ARMv8
+#define ISA_ARMv8_1a	ISA_ARMv8a, isa_bit_crc32, isa_bit_ARMv8_1
+#define ISA_ARMv8_2a	ISA_ARMv8_1a, isa_bit_ARMv8_2
+#define ISA_ARMv8m_base ISA_ARMv6m, isa_bit_ARMv8, isa_bit_cmse, isa_bit_tdiv
+#define ISA_ARMv8m_main ISA_ARMv7m, isa_bit_ARMv8, isa_bit_cmse
+
+/* List of all FPU bits to strip out if -mfpu is used to override the
+   default.  */
+#define ISA_ALL_FPU	isa_bit_VFPv2, isa_bit_VFPv3, isa_bit_neon
+
+/* Helper macro so that we can concatenate multiple features together
+   with arm-*.def files, since macro substitution can't have commas within an
+   argument that lacks parenthesis.  */
+#define ISA_FEAT(X)	X,
+#endif
diff --git a/gcc/config/arm/arm-opts.h b/gcc/config/arm/arm-opts.h
index 6f15065..a62ac46 100644
--- a/gcc/config/arm/arm-opts.h
+++ b/gcc/config/arm/arm-opts.h
@@ -31,7 +31,7 @@
 enum processor_type
 {
 #undef ARM_CORE
-#define ARM_CORE(NAME, INTERNAL_IDENT, IDENT, TUNE_FLAGS, ARCH, FLAGS, COSTS) \
+#define ARM_CORE(NAME, INTERNAL_IDENT, IDENT, TUNE_FLAGS, ARCH, ISA, FLAGS, COSTS) \
   TARGET_CPU_##INTERNAL_IDENT,
 #include "arm-cores.def"
 #undef ARM_CORE
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 2ec9a4e3..58d2ae3 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -23,6 +23,7 @@
 #define GCC_ARM_PROTOS_H
 
 #include "arm-flags.h"
+#include "arm-isa.h"
 
 extern enum unwind_info_type arm_except_unwind_info (struct gcc_options *);
 extern int use_return_insn (int, rtx);
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index b5e12dc..9d83379 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -325,12 +325,6 @@ EnumValue
 Enum(processor_type) String(cortex-a73) Value( TARGET_CPU_cortexa73)
 
 EnumValue
-Enum(processor_type) String(cortex-m23) Value( TARGET_CPU_cortexm23)
-
-EnumValue
-Enum(processor_type) String(cortex-m33) Value( TARGET_CPU_cortexm33)
-
-EnumValue
 Enum(processor_type) String(exynos-m1) Value( TARGET_CPU_exynosm1)
 
 EnumValue
@@ -354,6 +348,12 @@ Enum(processor_type) String(cortex-a73.cortex-a35) Value( TARGET_CPU_cortexa73co
 EnumValue
 Enum(processor_type) String(cortex-a73.cortex-a53) Value( TARGET_CPU_cortexa73cortexa53)
 
+EnumValue
+Enum(processor_type) String(cortex-m23) Value( TARGET_CPU_cortexm23)
+
+EnumValue
+Enum(processor_type) String(cortex-m33) Value( TARGET_CPU_cortexm33)
+
 Enum
 Name(arm_arch) Type(int)
 Known ARM architectures (for use with the -march= option):
@@ -443,28 +443,25 @@ EnumValue
 Enum(arm_arch) String(armv8.1-a) Value(27)
 
 EnumValue
-Enum(arm_arch) String(armv8.1-a+crc) Value(28)
-
-EnumValue
-Enum(arm_arch) String(armv8.2-a) Value(29)
+Enum(arm_arch) String(armv8.2-a) Value(28)
 
 EnumValue
-Enum(arm_arch) String(armv8.2-a+fp16) Value(30)
+Enum(arm_arch) String(armv8.2-a+fp16) Value(29)
 
 EnumValue
-Enum(arm_arch) String(armv8-m.base) Value(31)
+Enum(arm_arch) String(armv8-m.base) Value(30)
 
 EnumValue
-Enum(arm_arch) String(armv8-m.main) Value(32)
+Enum(arm_arch) String(armv8-m.main) Value(31)
 
 EnumValue
-Enum(arm_arch) String(armv8-m.main+dsp) Value(33)
+Enum(arm_arch) String(armv8-m.main+dsp) Value(32)
 
 EnumValue
-Enum(arm_arch) String(iwmmxt) Value(34)
+Enum(arm_arch) String(iwmmxt) Value(33)
 
 EnumValue
-Enum(arm_arch) String(iwmmxt2) Value(35)
+Enum(arm_arch) String(iwmmxt2) Value(34)
 
 Enum
 Name(arm_fpu) Type(int)
diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md
index 4c92927..22e4a53 100644
--- a/gcc/config/arm/arm-tune.md
+++ b/gcc/config/arm/arm-tune.md
@@ -34,8 +34,8 @@
 	cortexm3,marvell_pj4,cortexa15cortexa7,
 	cortexa17cortexa7,cortexa32,cortexa35,
 	cortexa53,cortexa57,cortexa72,
-	cortexa73,cortexm23,cortexm33,
-	exynosm1,falkor,qdf24xx,
-	xgene1,cortexa57cortexa53,cortexa72cortexa53,
-	cortexa73cortexa35,cortexa73cortexa53"
+	cortexa73,exynosm1,falkor,
+	qdf24xx,xgene1,cortexa57cortexa53,
+	cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,
+	cortexm23,cortexm33"
 	(const (symbol_ref "((enum attr_tune) arm_tune)")))
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 2caaba4..bf04a06 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -953,6 +953,7 @@ struct processors
   unsigned int tune_flags;
   const char *arch;
   enum base_architecture base_arch;
+  enum isa_feature isa_bits[isa_num_bits];
   const arm_feature_set flags;
   const struct tune_params *const tune;
 };
@@ -2288,12 +2289,13 @@ const struct tune_params arm_fa726te_tune =
 static const struct processors all_cores[] =
 {
   /* ARM Cores */
-#define ARM_CORE(NAME, X, IDENT, TUNE_FLAGS, ARCH, FLAGS, COSTS) \
+#define ARM_CORE(NAME, X, IDENT, TUNE_FLAGS, ARCH, ISA, FLAGS, COSTS)	\
   {NAME, TARGET_CPU_##IDENT, TUNE_FLAGS, #ARCH, BASE_ARCH_##ARCH, \
-   FLAGS, &arm_##COSTS##_tune},
+   {ISA isa_nobit}, FLAGS, &arm_##COSTS##_tune},
 #include "arm-cores.def"
 #undef ARM_CORE
-  {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, ARM_FSET_EMPTY, NULL}
+  {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, {isa_nobit},
+   ARM_FSET_EMPTY, NULL}
 };
 
 static const struct processors all_architectures[] =
@@ -2302,11 +2304,12 @@ static const struct processors all_architectures[] =
   /* We don't specify tuning costs here as it will be figured out
      from the core.  */
 
-#define ARM_ARCH(NAME, CORE, TUNE_FLAGS, ARCH, FLAGS)			\
-  {NAME, TARGET_CPU_##CORE, TUNE_FLAGS, #ARCH, BASE_ARCH_##ARCH, FLAGS, NULL},
+#define ARM_ARCH(NAME, CORE, TUNE_FLAGS, ARCH, ISA, FLAGS)		\
+  {NAME, TARGET_CPU_##CORE, TUNE_FLAGS, #ARCH, BASE_ARCH_##ARCH,	\
+  {ISA isa_nobit}, FLAGS, NULL},
 #include "arm-arches.def"
 #undef ARM_ARCH
-  {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, ARM_FSET_EMPTY, NULL}
+  {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, {isa_nobit}, ARM_FSET_EMPTY, NULL}
 };
 
 

