From patchwork Tue Nov 22 11:52:14 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Preudhomme X-Patchwork-Id: 83388 Delivered-To: patch@linaro.org Received: by 10.140.97.165 with SMTP id m34csp2050991qge; Tue, 22 Nov 2016 03:52:45 -0800 (PST) X-Received: by 10.98.196.89 with SMTP id y86mr25035561pff.172.1479815565822; Tue, 22 Nov 2016 03:52:45 -0800 (PST) Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id n24si28138255pgc.301.2016.11.22.03.52.45 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 22 Nov 2016 03:52:45 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-442208-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-442208-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-442208-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :references:subject:to:from:message-id:date:mime-version :in-reply-to:content-type; q=dns; s=default; b=hqlG41YqvTekHKaqW w3zmyL5WTx704MQII5mwwPAjc2qJv6XehvLPFaBaxc3B06+wvOauamYFOAQyZ8uP JlrRJ+dBCOrB6h0r72N7gQspX6dNcc/T+Tvc5E1G7PkMVAhG7X2GLK2bBKYXLqCP lHkpeTWu4bkVBAtRSNGITt//dY= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :references:subject:to:from:message-id:date:mime-version :in-reply-to:content-type; s=default; bh=HuD9QjA08RsMB2a7rAijL7i E6Jc=; b=dBShr2EYqPcxgzgCJ0OUYBeanFMs87uyrykJuBuvh2vYpe1QNAezvj2 hNXQZdpIvYVXkELjGQH/nPem9vr4E16MZisrt86WzQk/1zLqUvA8xRRik4xO1xuR +ioaKLwSrccZhbPmxwOFABNzMjD7Fgg2Ca7xp7PWapJfTM8aD/vY= Received: (qmail 126795 invoked by alias); 22 Nov 2016 11:52:29 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 126769 invoked by uid 89); 22 Nov 2016 11:52:29 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.9 required=5.0 tests=BAYES_00, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=0xf8, Best, our X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 22 Nov 2016 11:52:18 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4751D16; Tue, 22 Nov 2016 03:52:16 -0800 (PST) Received: from [10.2.206.52] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id ED4363F220 for ; Tue, 22 Nov 2016 03:52:15 -0800 (PST) References: <8361d384-28ff-6f29-a33a-83bfcd25b043@foss.arm.com> Subject: [arm-embedded] [PATCH, GCC/ARM, ping] Fix PR77904: callee-saved register trashed when clobbering sp To: "gcc-patches@gcc.gnu.org" From: Thomas Preudhomme X-Forwarded-Message-Id: <8361d384-28ff-6f29-a33a-83bfcd25b043@foss.arm.com> Message-ID: Date: Tue, 22 Nov 2016 11:52:14 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.3.0 MIME-Version: 1.0 In-Reply-To: <8361d384-28ff-6f29-a33a-83bfcd25b043@foss.arm.com> X-IsSubscribed: yes Hi, We have decided to backport this patch to fix callee-saved register corruption when clobbering sp to our embedded-6-branch. *** gcc/ChangeLog.arm *** PR target/77904 * config/arm/arm.c (thumb1_compute_save_reg_mask): Mark frame pointer in save register mask if it is needed. *** gcc/testsuite/ChangeLog.arm *** PR target/77904 * gcc.target/arm/pr77904.c: New test. Best regards, Thomas Ping? Best regards, Thomas On 03/11/16 16:52, Thomas Preudhomme wrote: > Hi, > > When using a callee-saved register to save the frame pointer the Thumb-1 > prologue fails to save the callee-saved register before that. For ARM and > Thumb-2 targets the frame pointer is handled as a special case but nothing is > done for Thumb-1 targets. This patch adds the same logic for Thumb-1 targets. > > ChangeLog entries are as follow: > > *** gcc/ChangeLog *** > > 2016-11-02 Thomas Preud'homme > > PR target/77904 > * config/arm/arm.c (thumb1_compute_save_reg_mask): mark frame pointer > in save register mask if it is needed. > > > *** gcc/testsuite/ChangeLog *** > > 2016-11-02 Thomas Preud'homme > > PR target/77904 > * gcc.target/arm/pr77904.c: New test. > > > Testing: Testsuite shows no regression when run with arm-none-eabi GCC > cross-compiler for Cortex-M0 target. > > Is this ok for trunk? > > Best regards, > > Thomas diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index dd8d5e5db8ca50daab648e58df290969aa794862..c7bf3320a3db5dfc4f33ae145ff2e5f239d6c0f9 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -19495,6 +19495,10 @@ thumb1_compute_save_reg_mask (void) if (df_regs_ever_live_p (reg) && callee_saved_reg_p (reg)) mask |= 1 << reg; + /* Handle the frame pointer as a special case. */ + if (frame_pointer_needed) + mask |= 1 << HARD_FRAME_POINTER_REGNUM; + if (flag_pic && !TARGET_SINGLE_PIC_BASE && arm_pic_register != INVALID_REGNUM diff --git a/gcc/testsuite/gcc.target/arm/pr77904.c b/gcc/testsuite/gcc.target/arm/pr77904.c new file mode 100644 index 0000000000000000000000000000000000000000..76728c07e73350ce44160cabff3dd2fa7a6ef021 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr77904.c @@ -0,0 +1,45 @@ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +__attribute__ ((noinline, noclone)) void +clobber_sp (void) +{ + __asm volatile ("" : : : "sp"); +} + +int +main (void) +{ + int ret; + + __asm volatile ("mov\tr4, #0xf4\n\t" + "mov\tr5, #0xf5\n\t" + "mov\tr6, #0xf6\n\t" + "mov\tr7, #0xf7\n\t" + "mov\tr0, #0xf8\n\t" + "mov\tr8, r0\n\t" + "mov\tr0, #0xfa\n\t" + "mov\tr10, r0" + : : : "r0", "r4", "r5", "r6", "r7", "r8", "r10"); + clobber_sp (); + + __asm volatile ("cmp\tr4, #0xf4\n\t" + "bne\tfail\n\t" + "cmp\tr5, #0xf5\n\t" + "bne\tfail\n\t" + "cmp\tr6, #0xf6\n\t" + "bne\tfail\n\t" + "cmp\tr7, #0xf7\n\t" + "bne\tfail\n\t" + "mov\tr0, r8\n\t" + "cmp\tr0, #0xf8\n\t" + "bne\tfail\n\t" + "mov\tr0, r10\n\t" + "cmp\tr0, #0xfa\n\t" + "bne\tfail\n\t" + "mov\t%0, #1\n" + "fail:\n\t" + "sub\tr0, #1" + : "=r" (ret) : :); + return ret; +}