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[209.132.180.131]) by mx.google.com with ESMTPS id 14si6975838pgc.38.2017.06.09.05.59.03 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Jun 2017 05:59:03 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-455533-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-455533-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-455533-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references:mime-version:content-type; q=dns; s= default; b=R6mgKSgRgkp4eKlbAM+DsWpiQ0ggFvwvCocD9OwdbJXWXszOu7NKo vyhzi+kmReTQGTxGIocgTQ8exaudMCHDu9zey8pby7lcw6dzJRJe/hA714pOJHhK P1E/OsnEPogPp7UkESHJTM/csHKg9pqNXAHZ9GihZJd2DWnjdBkGK8= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references:mime-version:content-type; s=default; bh=AuXl/xPnr+NML895Qbr1UCETVCY=; b=jnQj9KjP3AwFcwMQ9v6f32JtgVf6 h24ZosYnIvrSeWwTU7C4TMkk3+IsbP96kCyAjgY0KmWTasfYHtn4OuXVKsYMkW6j VoyMm8YAUNMb9qaojiLz1mLciaxrvgCoFFza/5QUyiU2iTIWBcxbGxQyxK5TuQfk JZJM51LHLYNWV74= Received: (qmail 94308 invoked by alias); 9 Jun 2017 12:54:53 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 85329 invoked by uid 89); 9 Jun 2017 12:54:35 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_SOFTFAIL autolearn=ham version=3.3.2 spammy= X-HELO: eggs.gnu.org Received: from eggs.gnu.org (HELO eggs.gnu.org) (208.118.235.92) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 09 Jun 2017 12:54:32 +0000 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dJJQt-0007k3-S8 for gcc-patches@gcc.gnu.org; Fri, 09 Jun 2017 08:54:33 -0400 Received: from foss.arm.com ([217.140.101.70]:47128) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dJJQt-0007Te-HX for gcc-patches@gcc.gnu.org; Fri, 09 Jun 2017 08:54:31 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3EB431610; Fri, 9 Jun 2017 05:54:31 -0700 (PDT) Received: from e105689-lin.cambridge.arm.com (e105689-lin.cambridge.arm.com [10.2.207.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C12523F3E1; Fri, 9 Jun 2017 05:54:30 -0700 (PDT) From: Richard Earnshaw To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw Subject: [PATCH 30/30] [arm][doc] Document changes to -mcpu, -mtune and -mfpu. Date: Fri, 9 Jun 2017 13:53:59 +0100 Message-Id: In-Reply-To: References: In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 This patch adds the remainder of the main documentation changes. It adds the changes for -mcpu, -mtune and -mfpu. I've chosen to document the extension options under -mcpu rather than under -mtune because, while they are permitted with -mtune, they do not affect the behaviour of the tuning done by the compiler. I've also inverted the sense of the table (making the primary index the extension name and then listing the CPU names to which it applies. This is because the extensions are much more orthoganal in meaning here and having a primary entry via the CPU name would lead to enormous duplication. Finally, it adds the relevant changes to -mfpu. I haven't stated yet that any setting of -mfpu other than 'auto' is deprecated, but that is certainly the long-term goal of this patch series. * doc/invoke.texi (ARM Options, -mcpu): Document supported extension options. (ARM Options, -mtune): Document that this accepts the same extension options as -mcpu. (ARM Options, -mfpu): Document addition of -mfpu=auto. --- gcc/doc/invoke.texi | 68 +++++++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 63 insertions(+), 5 deletions(-) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index d4c8726..a23ba6f 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -15490,12 +15490,15 @@ processors, balancing between optimizations that benefit some CPUs in the range, and avoiding performance pitfalls of other CPUs. The effects of this option may change in future GCC versions as CPU models come and go. +@option{-mtune} permits the same extension options as @option{-mcpu}, but +the extension options do not affect the tuning of the generated code. + @option{-mtune=native} causes the compiler to auto-detect the CPU of the build computer. At present, this feature is only supported on GNU/Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect. -@item -mcpu=@var{name} +@item -mcpu=@var{name@r{[}+extension@dots{}@r{]}} @opindex mcpu This specifies the name of the target ARM processor. GCC uses this name to derive the name of the target ARM architecture (as if specified @@ -15504,9 +15507,62 @@ performance (as if specified by @option{-mtune}). Where this option is used in conjunction with @option{-march} or @option{-mtune}, those options take precedence over the appropriate part of this option. +Many of the supported CPUs implement optional architectural +extensions. Where this is so the architectural extensions are +normally enabled by default. If implementations that lack the +extension exist, then the extension syntax can be used to disable +those extensions that have been omitted. For floating-point and +Advanced SIMD (Neon) instructions, the settings of the options +@option{-mfloat-abi} and @option{-mfpu} must also be considered: +floating-point and Advanced SIMD instructions will only be used if +@option{-mfloat-abi} is not set to @samp{soft}; and any setting of +@option{-mfpu} other than @samp{auto} will override the available +floating-point and SIMD extension instructions. + +For example, @samp{cortex-a9} can be found in three major +configurations: integer only, with just a floating-point unit or with +floating-point and Advanced SIMD. The default is to enable all the +instructions, but the extensions @samp{+nosimd} and @samp{+nofp} can +be used to disable just the SIMD or both the SIMD and floating-point +instructions respectively. + Permissible names for this option are the same as those for @option{-mtune}. +The following extension options are common to the listed CPUs: + +@table @samp +@item +nofp +Disables the floating-point instructions on @samp{arm9e}, +@samp{arm946e-s}, @samp{arm966e-s}, @samp{arm968e-s}, @samp{arm10e}, +@samp{arm1020e}, @samp{arm1022e}, @samp{arm926ej-s}, +@samp{arm1026ej-s}, @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8}, +@samp{cortex-m4}, @samp{cortex-m7} and @samp{cortex-m33}. +Disables the floating-point and SIMD instructions on +@samp{generic-armv7-a}, @samp{cortex-a5}, @samp{cortex-a7}, +@samp{cortex-a8}, @samp{cortex-a9}, @samp{cortex-a12}, +@samp{cortex-a15}, @samp{cortex-a17}, @samp{cortex-a15.cortex-a7}, +@samp{cortex-a17.cortex-a7}, @samp{cortex-a32}, @samp{cortex-a35} +and @samp{cortex-a53}. + +@item +nofp.dp +Disables the double-precision component of the floating-point instructions +on @samp{cortex-r5} and @samp{cortex-m7}. + +@item +nosimd +Disables the SIMD (but not floating-point) instructions on +@samp{generic-armv7-a}, @samp{cortex-a5}, @samp{cortex-a7} +and @samp{cortex-a9}. +@end table + +Additionally the @samp{generic-armv7-a} pseudo target defaults to +VFPv3 with 16 double-precision registers. It supports the following +extension options: @samp{vfpv3-d16}, @samp{vfpv3}, +@samp{vfpv3-d16-fp16}, @samp{vfpv3-fp16}, @samp{vfpv4-d16}, +@samp{vfpv4}, @samp{neon}, @samp{neon-vfpv3}, @samp{neon-fp16}, +@samp{neon-vfpv4}. The meanings are the same as for the extensions to +@option{-march=armv7-a}. + @option{-mcpu=generic-@var{arch}} is also permissible, and is equivalent to @option{-march=@var{arch} -mtune=generic-@var{arch}}. See @option{-mtune} for more information. @@ -15519,7 +15575,8 @@ is unsuccessful the option has no effect. @item -mfpu=@var{name} @opindex mfpu This specifies what floating-point hardware (or hardware emulation) is -available on the target. Permissible names are: @samp{vfpv2}, @samp{vfpv3}, +available on the target. Permissible names are: @samp{auto}, @samp{vfpv2}, +@samp{vfpv3}, @samp{vfpv3-fp16}, @samp{vfpv3-d16}, @samp{vfpv3-d16-fp16}, @samp{vfpv3xd}, @samp{vfpv3xd-fp16}, @samp{neon-vfpv3}, @samp{neon-fp16}, @samp{vfpv4}, @samp{vfpv4-d16}, @samp{fpv4-sp-d16}, @samp{neon-vfpv4}, @@ -15528,11 +15585,12 @@ available on the target. Permissible names are: @samp{vfpv2}, @samp{vfpv3}, Note that @samp{neon} is an alias for @samp{neon-vfpv3} and @samp{vfp} is an alias for @samp{vfpv2}. -If @option{-msoft-float} is specified this specifies the format of -floating-point values. +The setting @samp{auto} is the default and is special. It causes the +compiler to select the floating-point and Advanced SIMD instructions +based on the settings of @option{-mcpu} and @option{-march}. If the selected floating-point hardware includes the NEON extension -(e.g. @option{-mfpu}=@samp{neon}), note that floating-point +(e.g. @option{-mfpu=neon}), note that floating-point operations are not generated by GCC's auto-vectorization pass unless @option{-funsafe-math-optimizations} is also specified. This is because NEON hardware does not fully implement the IEEE 754 standard for