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[209.132.180.131]) by mx.google.com with ESMTPS id e85si14353362pfk.179.2016.10.13.05.54.42 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 13 Oct 2016 05:54:43 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-438505-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-438505-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-438505-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; q=dns; s=default; b=w3DwDjh2WRWFm5JXZkGZcUOe20gNTBsuCgePcqLGXvp/R+oaxf dwOaHuB4D5rK+aCTsAy8KDt474ieaPOHC0/rM5TKVXsPI7zfiwYeljJN1fmEqQig pFTzaoD98yIzFCKpNaqypIVHTkDWDH+gesgLRSuNspsP2lHCxAt8V2vFA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; s= default; bh=4fibEpI606iKSLo/SDjLG8950Vo=; b=ihO44HyjpszTsroygQ20 xRzeJUFBw8SAn+v3ZOEGIWJfTaSkm00jLqPzalLp6SpOCd+uKAixkUq4HjoGrIE4 cOnpK5wrWlwx6I44Q3PFGFfGpJY39zFsf3uL+fcuTjOlC7s0v7D0Amz0TUIkTpua /UyJLUtDIWc6/2N0JxEZdng= Received: (qmail 33487 invoked by alias); 13 Oct 2016 12:54:27 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 33476 invoked by uid 89); 13 Oct 2016 12:54:26 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.3 required=5.0 tests=BAYES_00, RP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 spammy=REV, FPU, FEATURES, 1930 X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 13 Oct 2016 12:54:16 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5FCCB29 for ; Thu, 13 Oct 2016 05:54:13 -0700 (PDT) Received: from e105689-lin.cambridge.arm.com (e105689-lin.cambridge.arm.com [10.2.207.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E1AE33F32C; Thu, 13 Oct 2016 05:54:12 -0700 (PDT) To: gcc-patches From: "Richard Earnshaw (lists)" Subject: [PATCH, ARM] Remove redundant model field from FPU descriptions Message-ID: Date: Thu, 13 Oct 2016 13:54:09 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.3.0 MIME-Version: 1.0 This is the first of a number of patches to clean up the FPU support on ARM. In the days when GCC for ARM supported both the VFP and FPA floating-point units, the fpu_model field in the FP architectures description described which type of floating point numbers the machine supported. Now that VFP is the only supported format, fpu_model is now redundant. This patch removes the now unnecessary code. Tested on arm-none-eabi, installed on trunk. * arm.h (TARGET_VFP): Unconditionally define to 1. (arm_fpu_desc): Remove 'model' field. (TARGET_FPU_MODEL): Delete. * arm.c (all_fpus): Don't initialize the model field. (arm_can_inline_p): Don't check the FPU model. * arm-fpus.def: Remove redundant model field from all FPU descriptions. diff --git a/gcc/config/arm/arm-fpus.def b/gcc/config/arm/arm-fpus.def index d340e26..e0c4365 100644 --- a/gcc/config/arm/arm-fpus.def +++ b/gcc/config/arm/arm-fpus.def @@ -19,30 +19,29 @@ /* Before using #include to read this file, define a macro: - ARM_FPU(NAME, MODEL, REV, VFP_REGS, FEATURES) + ARM_FPU(NAME, REV, VFP_REGS, FEATURES) The arguments are the fields of struct arm_fpu_desc. genopt.sh assumes no whitespace up to the first "," in each entry. */ -ARM_FPU("vfp", ARM_FP_MODEL_VFP, 2, VFP_REG_D16, FPU_FL_NONE) -ARM_FPU("vfpv3", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, FPU_FL_NONE) -ARM_FPU("vfpv3-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, FPU_FL_FP16) -ARM_FPU("vfpv3-d16", ARM_FP_MODEL_VFP, 3, VFP_REG_D16, FPU_FL_NONE) -ARM_FPU("vfpv3-d16-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_D16, FPU_FL_FP16) -ARM_FPU("vfpv3xd", ARM_FP_MODEL_VFP, 3, VFP_REG_SINGLE, FPU_FL_NONE) -ARM_FPU("vfpv3xd-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_SINGLE, FPU_FL_FP16) -ARM_FPU("neon", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, FPU_FL_NEON) -ARM_FPU("neon-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, FPU_FL_NEON | FPU_FL_FP16) -ARM_FPU("vfpv4", ARM_FP_MODEL_VFP, 4, VFP_REG_D32, FPU_FL_FP16) -ARM_FPU("vfpv4-d16", ARM_FP_MODEL_VFP, 4, VFP_REG_D16, FPU_FL_FP16) -ARM_FPU("fpv4-sp-d16", ARM_FP_MODEL_VFP, 4, VFP_REG_SINGLE, FPU_FL_FP16) -ARM_FPU("fpv5-sp-d16", ARM_FP_MODEL_VFP, 5, VFP_REG_SINGLE, FPU_FL_FP16) -ARM_FPU("fpv5-d16", ARM_FP_MODEL_VFP, 5, VFP_REG_D16, FPU_FL_FP16) -ARM_FPU("neon-vfpv4", ARM_FP_MODEL_VFP, 4, VFP_REG_D32, FPU_FL_NEON | FPU_FL_FP16) -ARM_FPU("fp-armv8", ARM_FP_MODEL_VFP, 8, VFP_REG_D32, FPU_FL_FP16) -ARM_FPU("neon-fp-armv8",ARM_FP_MODEL_VFP, 8, VFP_REG_D32, FPU_FL_NEON | FPU_FL_FP16) -ARM_FPU("crypto-neon-fp-armv8", - ARM_FP_MODEL_VFP, 8, VFP_REG_D32, FPU_FL_NEON | FPU_FL_FP16 | FPU_FL_CRYPTO) +ARM_FPU("vfp", 2, VFP_REG_D16, FPU_FL_NONE) +ARM_FPU("vfpv3", 3, VFP_REG_D32, FPU_FL_NONE) +ARM_FPU("vfpv3-fp16", 3, VFP_REG_D32, FPU_FL_FP16) +ARM_FPU("vfpv3-d16", 3, VFP_REG_D16, FPU_FL_NONE) +ARM_FPU("vfpv3-d16-fp16", 3, VFP_REG_D16, FPU_FL_FP16) +ARM_FPU("vfpv3xd", 3, VFP_REG_SINGLE, FPU_FL_NONE) +ARM_FPU("vfpv3xd-fp16", 3, VFP_REG_SINGLE, FPU_FL_FP16) +ARM_FPU("neon", 3, VFP_REG_D32, FPU_FL_NEON) +ARM_FPU("neon-fp16", 3, VFP_REG_D32, FPU_FL_NEON | FPU_FL_FP16) +ARM_FPU("vfpv4", 4, VFP_REG_D32, FPU_FL_FP16) +ARM_FPU("vfpv4-d16", 4, VFP_REG_D16, FPU_FL_FP16) +ARM_FPU("fpv4-sp-d16", 4, VFP_REG_SINGLE, FPU_FL_FP16) +ARM_FPU("fpv5-sp-d16", 5, VFP_REG_SINGLE, FPU_FL_FP16) +ARM_FPU("fpv5-d16", 5, VFP_REG_D16, FPU_FL_FP16) +ARM_FPU("neon-vfpv4", 4, VFP_REG_D32, FPU_FL_NEON | FPU_FL_FP16) +ARM_FPU("fp-armv8", 8, VFP_REG_D32, FPU_FL_FP16) +ARM_FPU("neon-fp-armv8", 8, VFP_REG_D32, FPU_FL_NEON | FPU_FL_FP16) +ARM_FPU("crypto-neon-fp-armv8", 8, VFP_REG_D32, FPU_FL_NEON | FPU_FL_FP16 | FPU_FL_CRYPTO) /* Compatibility aliases. */ -ARM_FPU("vfp3", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, FPU_FL_NONE) +ARM_FPU("vfp3", 3, VFP_REG_D32, FPU_FL_NONE) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 705fa00..49f4e2b 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -2334,8 +2334,8 @@ char arm_arch_name[] = "__ARM_ARCH_PROFILE__"; const struct arm_fpu_desc all_fpus[] = { -#define ARM_FPU(NAME, MODEL, REV, VFP_REGS, FEATURES) \ - { NAME, MODEL, REV, VFP_REGS, FEATURES }, +#define ARM_FPU(NAME, REV, VFP_REGS, FEATURES) \ + { NAME, REV, VFP_REGS, FEATURES }, #include "arm-fpus.def" #undef ARM_FPU }; @@ -30226,9 +30226,8 @@ arm_can_inline_p (tree caller, tree callee) if ((caller_fpu->features & callee_fpu->features) != callee_fpu->features) return false; - /* Need same model and regs. */ - if (callee_fpu->model != caller_fpu->model - || callee_fpu->regs != callee_fpu->regs) + /* Need same FPU regs. */ + if (callee_fpu->regs != callee_fpu->regs) return false; /* OK to inline between different modes. diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 35c72d3..7c4ea85 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -134,7 +134,8 @@ extern void (*arm_lang_output_object_attributes_hook)(void); #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT) /* Use hardware floating point calling convention. */ #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD) -#define TARGET_VFP (TARGET_FPU_MODEL == ARM_FP_MODEL_VFP) +/* We only support the VFP model these days. */ +#define TARGET_VFP (1) #define TARGET_IWMMXT (arm_arch_iwmmxt) #define TARGET_IWMMXT2 (arm_arch_iwmmxt2) #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT) @@ -363,7 +364,6 @@ enum vfp_reg_type extern const struct arm_fpu_desc { const char *name; - enum arm_fp_model model; int rev; enum vfp_reg_type regs; arm_fpu_feature_set features; @@ -372,7 +372,6 @@ extern const struct arm_fpu_desc /* Accessors. */ #define TARGET_FPU_NAME (all_fpus[arm_fpu_index].name) -#define TARGET_FPU_MODEL (all_fpus[arm_fpu_index].model) #define TARGET_FPU_REV (all_fpus[arm_fpu_index].rev) #define TARGET_FPU_REGS (all_fpus[arm_fpu_index].regs) #define TARGET_FPU_FEATURES (all_fpus[arm_fpu_index].features)