From patchwork Thu Dec 15 16:07:38 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Richard Earnshaw \(lists\)" X-Patchwork-Id: 88189 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp882140qgi; Thu, 15 Dec 2016 08:10:19 -0800 (PST) X-Received: by 10.99.251.69 with SMTP id w5mr3457758pgj.124.1481818219313; Thu, 15 Dec 2016 08:10:19 -0800 (PST) Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id 1si3152699pgu.53.2016.12.15.08.10.19 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Dec 2016 08:10:19 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-444531-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-444531-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-444531-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :subject:to:references:message-id:date:mime-version:in-reply-to :content-type; q=dns; s=default; b=e2s/Cyaonlah3ik46SKRlU+JKvGcC VI7yd6u2+5l7Hp8cPi0+IXgUEGXkNvudIYLfzUMxhy3TLDVQj67YWYR2NiVW/X14 VRKWORJNrpPxDJqzqp2hPZNYhGBlikSknHASAKhDYxAY1Gl/LgKxPUP1BJyw5xTw sUWIvFv45fio/g= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :subject:to:references:message-id:date:mime-version:in-reply-to :content-type; s=default; bh=Tzin3l8NnN0LY2eRW4XkB2rkpGE=; b=Tkx mr2IwcmaDl/cBx/YhCZUs6m/Thw6Q6uWKFcWt+QRESTWFULX06xdz7OM6bo6Ij+Z wHOd3OHK9LPW5Ti2CvzI7/1jnHTin0kL3PZgu+gJGFGuk8+NQ276jE1TMnu4O3YK JDzj1cer2MgfTDGAq+F6PwE8JF1qsIxiiL/mE+pQ= Received: (qmail 42253 invoked by alias); 15 Dec 2016 16:07:48 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 42188 invoked by uid 89); 15 Dec 2016 16:07:47 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-5.0 required=5.0 tests=BAYES_00, RP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 15 Dec 2016 16:07:41 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7A419154D; Thu, 15 Dec 2016 08:07:40 -0800 (PST) Received: from e105689-lin.cambridge.arm.com (e105689-lin.cambridge.arm.com [10.2.207.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 15B123F445 for ; Thu, 15 Dec 2016 08:07:39 -0800 (PST) From: "Richard Earnshaw (lists)" Subject: [PATCH 17/21] [arm] Use arm_active_target for most FP feature tests. To: gcc-patches@gcc.gnu.org References: Message-ID: Date: Thu, 15 Dec 2016 16:07:38 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.5.1 MIME-Version: 1.0 In-Reply-To: Now that the isa feature bits are all available in arm_active_target we can use that for most of the feature tests that are needed. * arm.h (TARGET_VFPD32): Use arm_active_target. (TARGET_VFP3): Likewise. (TARGET_VFP5): Likewise. (TARGET_VFP_SINGLE): Likewise. (TARGET_VFP_DOUBLE): Likewise. (TARGET_NEON_FP16): Likewise. (TARGET_FP16): Likewise. (TARGET_FMA): Likewise. (TARGET_FPU_ARMV8): Likewise. (TARGET_CRYPTO): Likewise. (TARGET_NEON): Likewise. (TARGET_FPU_FEATURES): Delete. * arm.c (arm_option_check_internal): Check for iwmmxt conflict with Neon using arm_active_target. --- gcc/config/arm/arm.c | 3 +-- gcc/config/arm/arm.h | 33 ++++++++++++++------------------- 2 files changed, 15 insertions(+), 21 deletions(-) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index df7a3ea..676c78b 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -2815,11 +2815,10 @@ static void arm_option_check_internal (struct gcc_options *opts) { int flags = opts->x_target_flags; - const struct arm_fpu_desc *fpu_desc = &all_fpus[opts->x_arm_fpu_index]; /* iWMMXt and NEON are incompatible. */ if (TARGET_IWMMXT - && ARM_FPU_FSET_HAS (fpu_desc->features, FPU_FL_NEON)) + && bitmap_bit_p (arm_active_target.isa, isa_bit_neon)) error ("iWMMXt and NEON are incompatible"); /* Make sure that the processor choice does not conflict with any of the diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 980bb74..17f030b 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -161,28 +161,27 @@ extern tree arm_fp16_type_node; to be more careful with TARGET_NEON as noted below. */ /* FPU is has the full VFPv3/NEON register file of 32 D registers. */ -#define TARGET_VFPD32 (TARGET_FPU_FEATURES & FPU_FL_D32) +#define TARGET_VFPD32 (bitmap_bit_p (arm_active_target.isa, isa_bit_fp_d32)) /* FPU supports VFPv3 instructions. */ -#define TARGET_VFP3 (TARGET_FPU_FEATURES & FPU_FL_VFPv3) +#define TARGET_VFP3 (bitmap_bit_p (arm_active_target.isa, isa_bit_VFPv3)) /* FPU supports FPv5 instructions. */ -#define TARGET_VFP5 (TARGET_FPU_FEATURES & FPU_FL_VFPv5) +#define TARGET_VFP5 (bitmap_bit_p (arm_active_target.isa, isa_bit_FPv5)) /* FPU only supports VFP single-precision instructions. */ -#define TARGET_VFP_SINGLE ((TARGET_FPU_FEATURES & FPU_FL_DBL) == 0) +#define TARGET_VFP_SINGLE (!TARGET_VFP_DOUBLE) /* FPU supports VFP double-precision instructions. */ -#define TARGET_VFP_DOUBLE (TARGET_FPU_FEATURES & FPU_FL_DBL) +#define TARGET_VFP_DOUBLE (bitmap_bit_p (arm_active_target.isa, isa_bit_fp_dbl)) /* FPU supports half-precision floating-point with NEON element load/store. */ #define TARGET_NEON_FP16 \ - (ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_NEON) \ - && ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_FP16)) + (bitmap_bit_p (arm_active_target.isa, isa_bit_neon) \ + && bitmap_bit_p (arm_active_target.isa, isa_bit_fp16conv)) -/* FPU supports VFP half-precision floating-point. */ -#define TARGET_FP16 \ - (ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_FP16)) +/* FPU supports VFP half-precision floating-point conversions. */ +#define TARGET_FP16 (bitmap_bit_p (arm_active_target.isa, isa_bit_fp16conv)) /* FPU supports converting between HFmode and DFmode in a single hardware step. */ @@ -190,14 +189,14 @@ extern tree arm_fp16_type_node; (TARGET_HARD_FLOAT && (TARGET_FP16 && TARGET_VFP5)) /* FPU supports fused-multiply-add operations. */ -#define TARGET_FMA (TARGET_FPU_FEATURES & FPU_FL_VFPv4) +#define TARGET_FMA (bitmap_bit_p (arm_active_target.isa, isa_bit_VFPv4)) /* FPU is ARMv8 compatible. */ -#define TARGET_FPU_ARMV8 (TARGET_FPU_FEATURES & FPU_FL_ARMv8) +#define TARGET_FPU_ARMV8 \ + (bitmap_bit_p (arm_active_target.isa, isa_bit_FP_ARMv8)) /* FPU supports Crypto extensions. */ -#define TARGET_CRYPTO \ - (ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_CRYPTO)) +#define TARGET_CRYPTO (bitmap_bit_p (arm_active_target.isa, isa_bit_crypto)) /* FPU supports Neon instructions. The setting of this macro gets revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT @@ -205,7 +204,7 @@ extern tree arm_fp16_type_node; available. */ #define TARGET_NEON \ (TARGET_32BIT && TARGET_HARD_FLOAT \ - && ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_NEON)) + && bitmap_bit_p (arm_active_target.isa, isa_bit_neon)) /* FPU supports ARMv8.1 Adv.SIMD extensions. */ #define TARGET_NEON_RDMA (TARGET_NEON && arm_arch8_1) @@ -367,10 +366,6 @@ extern const struct arm_fpu_desc arm_fpu_feature_set features; } all_fpus[]; -/* Accessors. */ - -#define TARGET_FPU_FEATURES (all_fpus[arm_fpu_index].features) - /* Which floating point hardware to schedule for. */ extern int arm_fpu_attr;