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Tue, 13 Dec 2016 11:51:42 +0000 Received: from SN2PR07MB2702.namprd07.prod.outlook.com (10.167.15.154) by CY1PR07MB2314.namprd07.prod.outlook.com (10.166.194.137) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.771.8; Tue, 13 Dec 2016 11:51:39 +0000 Received: from SN2PR07MB2702.namprd07.prod.outlook.com ([10.167.15.154]) by SN2PR07MB2702.namprd07.prod.outlook.com ([10.167.15.154]) with mapi id 15.01.0761.022; Tue, 13 Dec 2016 11:51:38 +0000 From: "Hurugalawadi, Naveen" To: Kyrill Tkachov , "gcc-patches@gcc.gnu.org" CC: "Pinski, Andrew" , James Greenhalgh , Marcus Shawcroft , Richard Earnshaw Subject: Re: [PATCH] [AArch64] Implement popcount pattern Date: Tue, 13 Dec 2016 11:51:37 +0000 Message-ID: References: , <584E81A9.8000402@foss.arm.com> In-Reply-To: <584E81A9.8000402@foss.arm.com> authentication-results: spf=none (sender IP is ) smtp.mailfrom=Naveen.Hurugalawadi@cavium.com; x-microsoft-exchange-diagnostics: 1; CY1PR07MB2314; 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Bootstrapped and Regression Tested on aarch64-thunderx-linux. >> The rest of the MD file uses the term AdvSIMD. Also, the instrurction >> is CNT rather than "pop count". Done. >> __builtin_popcount takes an unsigned int, so this should be >> scanning for absence of popcountsi2 instead? Done. Please find attached the modified patch as per review comments and let me know if its okay for Stage-1 or current branch. Thanks, Naveen diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 65eb326..0acb3f0 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3785,6 +3785,39 @@ } ) +;; Pop count be done via the "CNT" instruction in AdvSIMD. +;; +;; MOV v.1d, x0 +;; CNT v1.8b, v.8b +;; ADDV b2, v1.8b +;; MOV w0, v2.b[0] + +(define_expand "popcount2" + [(match_operand:GPI 0 "register_operand") + (match_operand:GPI 1 "register_operand")] + "TARGET_SIMD" +{ + rtx v = gen_reg_rtx (V8QImode); + rtx v1 = gen_reg_rtx (V8QImode); + rtx r = gen_reg_rtx (QImode); + rtx in = operands[1]; + rtx out = operands[0]; + if(mode == SImode) + { + rtx tmp; + tmp = gen_reg_rtx (DImode); + /* If we have SImode, zero extend to DImode, pop count does + not change if we have extra zeros. */ + emit_insn (gen_zero_extendsidi2 (tmp, in)); + in = tmp; + } + emit_move_insn (v, gen_lowpart (V8QImode, in)); + emit_insn (gen_popcountv8qi2 (v1, v)); + emit_insn (gen_reduc_plus_scal_v8qi (r, v1)); + emit_insn (gen_zero_extendqi2 (out, r)); + DONE; +}) + (define_insn "clrsb2" [(set (match_operand:GPI 0 "register_operand" "=r") (clrsb:GPI (match_operand:GPI 1 "register_operand" "r")))] diff --git a/gcc/testsuite/gcc.target/aarch64/popcnt.c b/gcc/testsuite/gcc.target/aarch64/popcnt.c new file mode 100644 index 0000000..37cf4b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/popcnt.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int +foo (int x) +{ + return __builtin_popcount (x); +} + +long +foo1 (int x) +{ + return __builtin_popcountl (x); +} + +/* { dg-final { scan-assembler-not "popcount" } } */ +/* { dg-final { scan-assembler-times "cnt\t" 2 } } */