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Tue, 08 Nov 2016 09:57:33 +0000 Received: from CO2PR07MB2694.namprd07.prod.outlook.com (10.166.214.7) by SN1PR07MB2319.namprd07.prod.outlook.com (10.169.127.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.707.6; Tue, 8 Nov 2016 09:57:30 +0000 Received: from CO2PR07MB2694.namprd07.prod.outlook.com ([10.166.214.7]) by CO2PR07MB2694.namprd07.prod.outlook.com ([10.166.214.7]) with mapi id 15.01.0707.006; Tue, 8 Nov 2016 09:57:29 +0000 From: "Hurugalawadi, Naveen" To: Kyrill Tkachov , "gcc-patches@gcc.gnu.org" CC: "Pinski, Andrew" , Marcus Shawcroft , Richard Earnshaw , James Greenhalgh Subject: Re: [PATCH] [AArch64] Fix PR71727 Date: Tue, 8 Nov 2016 09:57:29 +0000 Message-ID: References: , <5821940F.7060806@foss.arm.com> In-Reply-To: <5821940F.7060806@foss.arm.com> authentication-results: spf=none (sender IP is ) smtp.mailfrom=Naveen.Hurugalawadi@cavium.com; x-microsoft-exchange-diagnostics: 1; SN1PR07MB2319; 7:w/fBUd+1keLKhInU7LurojbofVmp2l5cN7cZhR/x/HD18dgNC225bDu+7ymqQxG+Uxa/LI4lk5YcoeIVhYdW89taioWo5CkTYox/AJbJBGlb65Wu6Zign2T8BKKanHbbEXHyg+lb7oUS0Munni2AmxUY9UEe+oJGmoWO5YDsFxm1pYj061LvlQfZrQEL//PQQLtq71cYsYuxoD9ZKh/IfLJbxWVh8GhL+jMDT4QTcHWxZDshbt3u9b3QI4sBQ/qW+63nCWkrvxB6R6Rzyje9d2O43M3Djs0QlM3+PpVFU/y4EpE0ZhByjcc2nBC721hyrQMbGOyj+Fzs1Epp0XawUH0EodN/nuByGjVQWin/aNU= x-forefront-antispam-report: SFV:SKI; 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SRVR:SN1PR07MB2319; BCL:0; PCL:0; RULEID:; SRVR:SN1PR07MB2319; x-forefront-prvs: 01208B1E18 received-spf: None (protection.outlook.com: cavium.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: cavium.com X-MS-Exchange-CrossTenant-originalarrivaltime: 08 Nov 2016 09:57:29.0443 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 711e4ccf-2e9b-4bcf-a551-4094005b6194 X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN1PR07MB2319 Hi Kyrill, Thanks for the review and suggestions. >> It's a good idea to CC the AArch64 maintainers and reviewers >> on aarch64 patches, or at least Thanks for CCing the maintainers. Added [AArch64] in the subject line. >> New functions need a function comment describing their arguments and their result. Done. >> Some more information about why the current behaviour is wrong >> and how the patch fixes it would be useful in reviewing. support_vector_misalignment target hook is incorrect when STRICT_ALIGNMENT is true for AArch64. The patch implements the hook and rectifies the behavior. Please find attached the modified patch as per suggestions. Thanks, Naveen diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index b7d4640..5a0eff5 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -141,6 +141,10 @@ static bool aarch64_vector_mode_supported_p (machine_mode); static bool aarch64_vectorize_vec_perm_const_ok (machine_mode vmode, const unsigned char *sel); static int aarch64_address_cost (rtx, machine_mode, addr_space_t, bool); +static bool aarch64_builtin_support_vector_misalignment (machine_mode mode, + const_tree type, + int misalignment, + bool is_packed); /* Major revision number of the ARM Architecture implemented by the target. */ unsigned aarch64_architecture_version; @@ -11148,6 +11152,37 @@ aarch64_simd_vector_alignment_reachable (const_tree type, bool is_packed) return true; } +/* Return true if the vector misalignment factor is supported by the + target. */ +static bool +aarch64_builtin_support_vector_misalignment (machine_mode mode, + const_tree type, int misalignment, + bool is_packed) +{ + if (TARGET_SIMD && STRICT_ALIGNMENT) + { + /* Return if movmisalign pattern is not supported for this mode. */ + if (optab_handler (movmisalign_optab, mode) == CODE_FOR_nothing) + return false; + + if (misalignment == -1) + { + /* Misalignment factor is unknown at compile time but we know + it's word aligned. */ + if (aarch64_simd_vector_alignment_reachable (type, is_packed)) + { + int element_size = TREE_INT_CST_LOW (TYPE_SIZE (type)); + + if (element_size != 64) + return true; + } + return false; + } + } + return default_builtin_support_vector_misalignment (mode, type, misalignment, + is_packed); +} + /* If VALS is a vector constant that can be loaded into a register using DUP, generate instructions to do so and return an RTX to assign to the register. Otherwise return NULL_RTX. */ @@ -14398,6 +14433,10 @@ aarch64_optab_supported_p (int op, machine_mode mode1, machine_mode, #undef TARGET_VECTOR_MODE_SUPPORTED_P #define TARGET_VECTOR_MODE_SUPPORTED_P aarch64_vector_mode_supported_p +#undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT +#define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \ + aarch64_builtin_support_vector_misalignment + #undef TARGET_ARRAY_MODE_SUPPORTED_P #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p diff --git a/gcc/testsuite/gcc.target/aarch64/pr71727.c b/gcc/testsuite/gcc.target/aarch64/pr71727.c new file mode 100644 index 0000000..05eef3e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr71727.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-options "-mstrict-align -O3" } */ + +struct test_struct_s +{ + long a; + long b; + long c; + long d; + unsigned long e; +}; + + +char _a; +struct test_struct_s xarray[128]; + +void +_start (void) +{ + struct test_struct_s *new_entry; + + new_entry = &xarray[0]; + new_entry->a = 1; + new_entry->b = 2; + new_entry->c = 3; + new_entry->d = 4; + new_entry->e = 5; + + return; +} + +/* { dg-final { scan-assembler-times "mov\tx" 5 {target lp64} } } */ +/* { dg-final { scan-assembler-not "add\tx0, x0, :" {target lp64} } } */