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Fri, 09 Dec 2016 07:02:15 +0000 Received: from CO2PR07MB2694.namprd07.prod.outlook.com (10.166.214.7) by BY2PR07MB2309.namprd07.prod.outlook.com (10.166.114.135) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.761.9; Fri, 9 Dec 2016 07:02:12 +0000 Received: from CO2PR07MB2694.namprd07.prod.outlook.com ([10.166.214.7]) by CO2PR07MB2694.namprd07.prod.outlook.com ([10.166.214.7]) with mapi id 15.01.0771.010; Fri, 9 Dec 2016 07:02:11 +0000 From: "Hurugalawadi, Naveen" To: "gcc-patches@gcc.gnu.org" CC: "Pinski, Andrew" , James Greenhalgh , Marcus Shawcroft , Richard Earnshaw Subject: Re: [PATCH] [AArch64] PR target/71663 Improve Vector Initializtion Date: Fri, 9 Dec 2016 07:02:11 +0000 Message-ID: References: In-Reply-To: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Naveen.Hurugalawadi@cavium.com; x-microsoft-exchange-diagnostics: 1; BY2PR07MB2309; 7:kVFzEKX0LbV362vw7Nu+kKPwvQ9ZJ299wlpGmcGJzM9FuS78zGXEchDmEcgwKkY0xUp48yhj0z7k9oas8uaXyrDcdb6GhjY18AWnHk6juzqBpy7LV30iVh9HksIMeJ/GeojK0fbDsLzmhApC20gplAllN4OggYou1NCLlmEcRqAaR23+ZJb9B68/wL3d9LIFN6poNZbPqEshLxNj/iSMgcO7KeSIvwyATWA2kIcQ+cU4NjL5dv/F13I20fukAfk6guIGgbObPhioYyw5IZMLd5qhfBQ6IJAlSIaHYajt+FwRTnCS4SWHMQ9f4t2lX43HT/cZShvzgjjuRcZP4vhmb/FSOk8+DS/S6KW80M63WFxRlzWjzHc/aKdryFSP9umlwxEPUG+pinO4MbMRqzCpauys8Y6bUHwkSj5KBw/8s4yd8Tya8fvBrEaBGZ0shzvqO0mDihep3cul6F/17io/AA== x-forefront-antispam-report: SFV:SKI; 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PCL:0; RULEID:(102415395)(6040375)(601004)(2401047)(5005006)(8121501046)(10201501046)(3002001)(6041248)(20161123555025)(20161123560025)(20161123562025)(20161123558021)(20161123564025)(6072148); SRVR:BY2PR07MB2309; BCL:0; PCL:0; RULEID:; SRVR:BY2PR07MB2309; x-forefront-prvs: 015114592F received-spf: None (protection.outlook.com: cavium.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: cavium.com X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Dec 2016 07:02:11.7586 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 711e4ccf-2e9b-4bcf-a551-4094005b6194 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY2PR07MB2309 Hi, Sorry. Missed out the testcase in patch submission. Added the missing testcase along with the ChangeLog. Please review the same and let us know if thats okay? 2016-12-09  Andrew PInski  gcc         * config/aarch64/aarch64.c (aarch64_expand_vector_init):         Improve vector initialization code gen. gcc/testsuite * gcc.target/aarch64/pr71663.c: New Testcase. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index e87831f..da5b6fa 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -11609,11 +11609,54 @@ aarch64_expand_vector_init (rtx target, rtx vals) aarch64_expand_vector_init (target, copy); } - /* Insert the variable lanes directly. */ - enum insn_code icode = optab_handler (vec_set_optab, mode); gcc_assert (icode != CODE_FOR_nothing); + /* If there is only varables, try to optimize + the inseration using dup for the most common element + followed by insertations. */ + if (n_var == n_elts && n_elts <= 16) + { + int matches[16][2]; + int nummatches = 0; + memset (matches, 0, sizeof(matches)); + for(int i = 0; i < n_elts; i++) + { + for (int j = 0; j <= i; j++) + { + if (rtx_equal_p (XVECEXP (vals, 0, i), XVECEXP (vals, 0, j))) + { + matches[i][0] = j; + matches[j][1]++; + if (i != j) + nummatches++; + break; + } + } + } + int maxelement = 0; + int maxv = 0; + for (int i = 0; i < n_elts; i++) + if (matches[i][1] > maxv) + maxelement = i, maxv = matches[i][1]; + + /* Create a duplicate of the most common element. */ + rtx x = copy_to_mode_reg (inner_mode, XVECEXP (vals, 0, maxelement)); + aarch64_emit_move (target, gen_rtx_VEC_DUPLICATE (mode, x)); + /* Insert the rest. */ + for (int i = 0; i < n_elts; i++) + { + rtx x = XVECEXP (vals, 0, i); + if (matches[i][0] == maxelement) + continue; + x = copy_to_mode_reg (inner_mode, x); + emit_insn (GEN_FCN (icode) (target, x, GEN_INT (i))); + } + return; + } + + /* Insert the variable lanes directly. */ + for (int i = 0; i < n_elts; i++) { rtx x = XVECEXP (vals, 0, i); diff --git a/gcc/testsuite/gcc.target/aarch64/pr71663.c b/gcc/testsuite/gcc.target/aarch64/pr71663.c new file mode 100644 index 0000000..c8df847 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr71663.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +#define vector __attribute__((vector_size(16))) + +vector float combine (float a, float b, float c, float d) +{ + return (vector float) { a, b, c, d }; +} + +/* { dg-final { scan-assembler-not "movi\t" } } */ +/* { dg-final { scan-assembler-not "orr\t" } } */ +/* { dg-final { scan-assembler-times "ins\t" 3 } } */ +/* { dg-final { scan-assembler-times "dup\t" 1 } } */