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Wed, 23 Nov 2016 05:26:02 +0000 Received: from CO2PR07MB2694.namprd07.prod.outlook.com (10.166.214.7) by BY2PR07MB2309.namprd07.prod.outlook.com (10.166.114.135) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.734.8; Wed, 23 Nov 2016 05:25:45 +0000 Received: from CO2PR07MB2694.namprd07.prod.outlook.com ([10.166.214.7]) by CO2PR07MB2694.namprd07.prod.outlook.com ([10.166.214.7]) with mapi id 15.01.0734.014; Wed, 23 Nov 2016 05:25:44 +0000 From: "Hurugalawadi, Naveen" To: "gcc-patches@gcc.gnu.org" CC: Richard Earnshaw , Marcus Shawcroft , "Pinski, Andrew" Subject: [PATCH] [AArch64] Fix PR71112 Date: Wed, 23 Nov 2016 05:25:44 +0000 Message-ID: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Naveen.Hurugalawadi@cavium.com; x-microsoft-exchange-diagnostics: 1; BY2PR07MB2309; 7:kI0FELJZVXd5qBfJI81sVjBiDEkgDhluatULUfg1uo5wV8gqhFKh/HL7jsuuW5xCsSyy//LrDLeYONOrv8sSBWSZAEQwZzL/eQd/y2ZRvl/LCVlKTWOqbAfUnZDa6rXFvTxhTePR+8Y6Zs+CbXHNOKa8XlhJ+gjqxlEz+5C3wE7TW1gyNWoez6gpFeobxiUSvMX/ewYlWdh99gl5gWSLqBC8P6qnIiknfaTOEMbWFF2o/bzIU4tfWEDy1zIDZrjUBOfi5S7fviHAUvy2nbPWbLH188+YAmZebc53oV2kIgWKvPm5PmAmNiLJSPZEPLnViTOcDoGfsvnwhbN8UMeECIhxKUSDDCl5wAKmj5rJIlw= x-forefront-antispam-report: SFV:SKI; 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SRVR:BY2PR07MB2309; BCL:0; PCL:0; RULEID:; SRVR:BY2PR07MB2309; x-forefront-prvs: 013568035E received-spf: None (protection.outlook.com: cavium.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: cavium.com X-MS-Exchange-CrossTenant-originalarrivaltime: 23 Nov 2016 05:25:44.2090 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 711e4ccf-2e9b-4bcf-a551-4094005b6194 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY2PR07MB2309 Hi, Please find attached the patch that fixes PR71112. The current implementation that handles SYMBOL_SMALL_GOT_28K in aarch64_load_symref_appropriately access the high part of RTX for Big-Endian mode which results in ICE for ILP32. The attached patch modifies it by accessing the lower part for both Endian and fixes the issue. Please review the patch and let me know if its okay? 2016-11-23 Andrew PInski gcc * config/aarch64/aarch64.c (aarch64_load_symref_appropriately): Access the lower part of RTX appropriately. gcc/testsuite * gcc.target/aarch64/pr71112.c : New Testcase. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index efcba83..4d87953 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -1298,7 +1298,8 @@ aarch64_load_symref_appropriately (rtx dest, rtx imm, emit_move_insn (gp_rtx, gen_rtx_HIGH (Pmode, s)); if (mode != GET_MODE (gp_rtx)) - gp_rtx = simplify_gen_subreg (mode, gp_rtx, GET_MODE (gp_rtx), 0); + gp_rtx = gen_lowpart (mode, gp_rtx); + } if (mode == ptr_mode) diff --git a/gcc/testsuite/gcc.target/aarch64/pr71112.c b/gcc/testsuite/gcc.target/aarch64/pr71112.c new file mode 100644 index 0000000..5bb9dee --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr71112.c @@ -0,0 +1,12 @@ +/* PR target/71112 */ +/* { dg-do compile } */ +/* { dg-options "-mabi=ilp32 -mbig-endian -fpie" } */ + +extern int dbs[100]; +void f (int *); +int +nscd_init (void) +{ + f (dbs); + return 0; +}