From patchwork Thu Jun 18 19:17:41 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Lyon X-Patchwork-Id: 50056 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wi0-f199.google.com (mail-wi0-f199.google.com [209.85.212.199]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 5854122903 for ; Thu, 18 Jun 2015 19:18:08 +0000 (UTC) Received: by wizw5 with SMTP id w5sf701094wiz.2 for ; Thu, 18 Jun 2015 12:18:07 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:mailing-list:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:sender :delivered-to:mime-version:date:message-id:subject:from:to :content-type:x-original-sender:x-original-authentication-results; bh=/qIhEGZq5+4Gk2O4oEz21tFU3NHgQevs+sLArzs47j4=; b=BqElCwvFtwheuvGitIGm5QS//da2yEu94zimSa5Z4xZKR+oqS9TZIwSe8lGRmoYndw ADYo1/9wCC4eDCPqAnkw02knlA5DSstAgnPnSYDNnA2GOYI94/PND2RXb6BMyVLXsa2t Tv/ExMxAJ1l+CYQdPU1gyRpoDRE7NHk+ZpOAbFVaP0eREZZqhkuU4XNQpxdjit2GZFaI NALVqQ0zJoOpLX+X2TfTfg+yY2SmFn9LnXCmuWwu4Mdq7mW4K7NyRzdo0DIdZvWxG6wd AQMo/tMBTgcVXgD2js+mtWwwtD3HICAAYQMPfA7I6xZNN7Ztj/DRo8fN9TVJ4ifLDv2q zLJg== X-Gm-Message-State: ALoCoQlXvRUsD1aHiLIFDWCiNgfditukFVXm7DLQHJGOC0JhEDKwfJl6oUneRtOk8hx42vSnzl1H X-Received: by 10.152.42.208 with SMTP id q16mr11547256lal.9.1434655087637; Thu, 18 Jun 2015 12:18:07 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.9.200 with SMTP id c8ls520882lab.81.gmail; Thu, 18 Jun 2015 12:18:07 -0700 (PDT) X-Received: by 10.152.27.74 with SMTP id r10mr14431762lag.31.1434655087347; Thu, 18 Jun 2015 12:18:07 -0700 (PDT) Received: from mail-la0-x230.google.com (mail-la0-x230.google.com. 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[209.132.180.131]) by mx.google.com with ESMTPS id sm5si12537063pac.38.2015.06.18.12.18.04 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 18 Jun 2015 12:18:05 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-400770-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 102200 invoked by alias); 18 Jun 2015 19:17:49 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 102125 invoked by uid 89); 18 Jun 2015 19:17:48 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.1 required=5.0 tests=AWL, BAYES_00, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=no version=3.3.2 X-HELO: mail-qg0-f43.google.com Received: from mail-qg0-f43.google.com (HELO mail-qg0-f43.google.com) (209.85.192.43) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Thu, 18 Jun 2015 19:17:44 +0000 Received: by qgeu36 with SMTP id u36so29470585qge.2 for ; Thu, 18 Jun 2015 12:17:42 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.140.36.137 with SMTP id p9mr16653605qgp.16.1434655061885; Thu, 18 Jun 2015 12:17:41 -0700 (PDT) Received: by 10.140.102.164 with HTTP; Thu, 18 Jun 2015 12:17:41 -0700 (PDT) Date: Thu, 18 Jun 2015 21:17:41 +0200 Message-ID: Subject: [PATCH][AArch64] Backport PR62308 to 4.9 From: Christophe Lyon To: "gcc-patches@gcc.gnu.org" X-IsSubscribed: yes X-Original-Sender: christophe.lyon@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c03::230 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 Hi, I backported the fix for PR62308 to 4.9-branch. The original patch applies cleanly. Bootstrap + make check OK on x86_64 and aarch64. I'm also adding the testcase I've just sent separately for trunk. OK? Christophe. 2015-06-18 Christophe Lyon Backport from mainline r215707. 2014-09-30 David Sherwood * ira-int.h (ira_allocno): Add "wmode" field. * ira-build.c (create_insn_allocnos): Add new "parent" function parameter. * ira-conflicts.c (ira_build_conflicts): Add conflicts for registers that cannot be accessed in wmode. Backport from mainline. 2015-06-18 Christophe Lyon * gcc.target/aarch64/pr62308.c: New test. [my mailer seems to break the ChangeLog indentation] Index: gcc/ira-conflicts.c =================================================================== --- gcc/ira-conflicts.c (revision 215706) +++ gcc/ira-conflicts.c (revision 215707) @@ -774,6 +774,27 @@ temp_hard_reg_set); } + /* Now we deal with paradoxical subreg cases where certain registers + cannot be accessed in the widest mode. */ + enum machine_mode outer_mode = ALLOCNO_WMODE (a); + enum machine_mode inner_mode = ALLOCNO_MODE (a); + if (GET_MODE_SIZE (outer_mode) > GET_MODE_SIZE (inner_mode)) + { + enum reg_class aclass = ALLOCNO_CLASS (a); + for (int j = ira_class_hard_regs_num[aclass] - 1; j >= 0; --j) + { + int inner_regno = ira_class_hard_regs[aclass][j]; + int outer_regno = simplify_subreg_regno (inner_regno, + inner_mode, 0, + outer_mode); + if (outer_regno < 0 + || !in_hard_reg_set_p (reg_class_contents[aclass], + outer_mode, outer_regno)) + SET_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj), + inner_regno); + } + } + if (ALLOCNO_CALLS_CROSSED_NUM (a) != 0) { int regno; Index: gcc/ChangeLog =================================================================== --- gcc/ChangeLog (revision 215706) +++ gcc/ChangeLog (revision 215707) @@ -1,3 +1,11 @@ +2014-09-30 David Sherwood + + * ira-int.h (ira_allocno): Add "wmode" field. + * ira-build.c (create_insn_allocnos): Add new "parent" function + parameter. + * ira-conflicts.c (ira_build_conflicts): Add conflicts for registers + that cannot be accessed in wmode. + 2014-09-30 Markus Trippelsdorf * data-streamer.c (bp_unpack_var_len_int): Avoid signed Index: gcc/ira-int.h =================================================================== --- gcc/ira-int.h (revision 215706) +++ gcc/ira-int.h (revision 215707) @@ -283,6 +283,9 @@ /* Mode of the allocno which is the mode of the corresponding pseudo-register. */ ENUM_BITFIELD (machine_mode) mode : 8; + /* Widest mode of the allocno which in at least one case could be + for paradoxical subregs where wmode > mode. */ + ENUM_BITFIELD (machine_mode) wmode : 8; /* Register class which should be used for allocation for given allocno. NO_REGS means that we should use memory. */ ENUM_BITFIELD (reg_class) aclass : 16; @@ -315,7 +318,7 @@ number (0, ...) - 2. Value -1 is used for allocnos spilled by the reload (at this point pseudo-register has only one allocno) which did not get stack slot yet. */ - short int hard_regno; + int hard_regno : 16; /* Allocnos with the same regno are linked by the following member. Allocnos corresponding to inner loops are first in the list (it corresponds to depth-first traverse of the loops). */ @@ -436,6 +439,7 @@ #define ALLOCNO_BAD_SPILL_P(A) ((A)->bad_spill_p) #define ALLOCNO_ASSIGNED_P(A) ((A)->assigned_p) #define ALLOCNO_MODE(A) ((A)->mode) +#define ALLOCNO_WMODE(A) ((A)->wmode) #define ALLOCNO_PREFS(A) ((A)->allocno_prefs) #define ALLOCNO_COPIES(A) ((A)->allocno_copies) #define ALLOCNO_HARD_REG_COSTS(A) ((A)->hard_reg_costs) Index: gcc/ira-build.c =================================================================== --- gcc/ira-build.c (revision 215706) +++ gcc/ira-build.c (revision 215707) @@ -524,6 +524,7 @@ ALLOCNO_BAD_SPILL_P (a) = false; ALLOCNO_ASSIGNED_P (a) = false; ALLOCNO_MODE (a) = (regno < 0 ? VOIDmode : PSEUDO_REGNO_MODE (regno)); + ALLOCNO_WMODE (a) = ALLOCNO_MODE (a); ALLOCNO_PREFS (a) = NULL; ALLOCNO_COPIES (a) = NULL; ALLOCNO_HARD_REG_COSTS (a) = NULL; @@ -893,6 +894,7 @@ parent = ALLOCNO_LOOP_TREE_NODE (a)->parent; cap = ira_create_allocno (ALLOCNO_REGNO (a), true, parent); ALLOCNO_MODE (cap) = ALLOCNO_MODE (a); + ALLOCNO_WMODE (cap) = ALLOCNO_WMODE (a); aclass = ALLOCNO_CLASS (a); ira_set_allocno_class (cap, aclass); ira_create_allocno_objects (cap); @@ -1859,9 +1861,9 @@ /* This recursive function creates allocnos corresponding to pseudo-registers containing in X. True OUTPUT_P means that X is - a lvalue. */ + an lvalue. PARENT corresponds to the parent expression of X. */ static void -create_insn_allocnos (rtx x, bool output_p) +create_insn_allocnos (rtx x, rtx outer, bool output_p) { int i, j; const char *fmt; @@ -1876,7 +1878,15 @@ ira_allocno_t a; if ((a = ira_curr_regno_allocno_map[regno]) == NULL) - a = ira_create_allocno (regno, false, ira_curr_loop_tree_node); + { + a = ira_create_allocno (regno, false, ira_curr_loop_tree_node); + if (outer != NULL && GET_CODE (outer) == SUBREG) + { + enum machine_mode wmode = GET_MODE (outer); + if (GET_MODE_SIZE (wmode) > GET_MODE_SIZE (ALLOCNO_WMODE (a))) + ALLOCNO_WMODE (a) = wmode; + } + } ALLOCNO_NREFS (a)++; ALLOCNO_FREQ (a) += REG_FREQ_FROM_BB (curr_bb); @@ -1887,25 +1897,25 @@ } else if (code == SET) { - create_insn_allocnos (SET_DEST (x), true); - create_insn_allocnos (SET_SRC (x), false); + create_insn_allocnos (SET_DEST (x), NULL, true); + create_insn_allocnos (SET_SRC (x), NULL, false); return; } else if (code == CLOBBER) { - create_insn_allocnos (XEXP (x, 0), true); + create_insn_allocnos (XEXP (x, 0), NULL, true); return; } else if (code == MEM) { - create_insn_allocnos (XEXP (x, 0), false); + create_insn_allocnos (XEXP (x, 0), NULL, false); return; } else if (code == PRE_DEC || code == POST_DEC || code == PRE_INC || code == POST_INC || code == POST_MODIFY || code == PRE_MODIFY) { - create_insn_allocnos (XEXP (x, 0), true); - create_insn_allocnos (XEXP (x, 0), false); + create_insn_allocnos (XEXP (x, 0), NULL, true); + create_insn_allocnos (XEXP (x, 0), NULL, false); return; } @@ -1913,10 +1923,10 @@ for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) { if (fmt[i] == 'e') - create_insn_allocnos (XEXP (x, i), output_p); + create_insn_allocnos (XEXP (x, i), x, output_p); else if (fmt[i] == 'E') for (j = 0; j < XVECLEN (x, i); j++) - create_insn_allocnos (XVECEXP (x, i, j), output_p); + create_insn_allocnos (XVECEXP (x, i, j), x, output_p); } } @@ -1935,7 +1945,7 @@ ira_assert (bb != NULL); FOR_BB_INSNS_REVERSE (bb, insn) if (NONDEBUG_INSN_P (insn)) - create_insn_allocnos (PATTERN (insn), false); + create_insn_allocnos (PATTERN (insn), NULL, false); /* It might be a allocno living through from one subloop to another. */ EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (bb), FIRST_PSEUDO_REGISTER, i, bi)