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[209.132.180.131]) by mx.google.com with ESMTPS id o8si19629531pad.129.2016.05.19.04.54.46 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 19 May 2016 04:54:46 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-427731-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-427731-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-427731-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:in-reply-to:references:date:message-id:subject :from:to:cc:content-type; q=dns; s=default; b=kFB576tNHNDuUV7qf7 mKPgyw2Gb73VdMNZsYo6knSAM/JXChk3d31pXW4Im+NynQp5sKIa/rPzInJesitf YAJgxVyz0IEiSU6V0gpkUgMhSGHZkZ32S1cro4iuiYXDBChLtzq2lv8lZ/lLUPce a6KzBNFRNLHPzxM3G9+zdEcxU= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:in-reply-to:references:date:message-id:subject :from:to:cc:content-type; s=default; bh=dpBR0VV5YFSCwzBLjJ0y+ndf JIY=; b=Yq6vp+5fwC26ltOkL0KNYB2hXBO1GXlPCCCehux+e14Q3GSHtypamBwj LKUpv3lS0xiPJHmQfoBS+hjksg4mkoy4GgegDG4Ky7sWzEFdkl5phLHKlJ9loxRR MCkZXP72gs4tm5W/o/O+dgJ29iFwwsrxwpkLUTr+w1eXhxv16m4= Received: (qmail 117892 invoked by alias); 19 May 2016 11:54:30 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 117124 invoked by uid 89); 19 May 2016 11:54:29 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.3 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 spammy=3219, spinning X-HELO: mail-qg0-f41.google.com Received: from mail-qg0-f41.google.com (HELO mail-qg0-f41.google.com) (209.85.192.41) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Thu, 19 May 2016 11:54:19 +0000 Received: by mail-qg0-f41.google.com with SMTP id w36so41539474qge.3 for ; Thu, 19 May 2016 04:54:19 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc; bh=bW8UusUdOcPBIcfdSHxv5zd+tcephAgFzSUfnNC0/GQ=; b=TD3n12rjDWilFqZ6oL7KULsDFsiXW2NsyxVMfSbwfBCIjt2V1R7Mr0tvCzl3488egW ekSKMRpAnj8Bw4VcRawFdLMq99ALhEGFz3kx9rbfd+fvLuuyH5rUNaMIlPxoq0jwkrCi TnyPNOUJGGa8n4FVtxfxyBRuKGg19UbR6PeWPFWBvI8Bh+4V0LJXgBXvvuRuCa03WXeQ pba6x8YT7N4y71UFXebT05fhFwNvLduDjcwxdjFrk/P9le5MJJJAL9zHEglOgquLENZm Gm1am08kKaQXpNafFyNgBQ37xZ6T5XBXDtudTAMSi5H6MkBhhhsRsUFi82ktACcUoXPm pxhQ== X-Gm-Message-State: AOPr4FXy6sEgfJcMgGG/oNAvtVLGuPa2H2xvYMBjpe/CPsXAYxfU+OcGxwFGbsBSAO1LP4tp1zT6wlLUnzEmg1/u MIME-Version: 1.0 X-Received: by 10.140.154.198 with SMTP id a189mr436550qha.8.1463658857568; Thu, 19 May 2016 04:54:17 -0700 (PDT) Received: by 10.140.99.73 with HTTP; Thu, 19 May 2016 04:54:17 -0700 (PDT) In-Reply-To: <20160513144748.GD12266@arm.com> References: <1462973041-7911-1-git-send-email-christophe.lyon@linaro.org> <1462973041-7911-7-git-send-email-christophe.lyon@linaro.org> <20160513143709.GB12266@arm.com> <20160513144748.GD12266@arm.com> Date: Thu, 19 May 2016 13:54:17 +0200 Message-ID: Subject: Re: [Patch ARM/AArch64 06/11] Add missing vtst_p8 and vtstq_p8 tests. From: Christophe Lyon To: James Greenhalgh Cc: "gcc-patches@gcc.gnu.org" , nd X-IsSubscribed: yes On 13 May 2016 at 16:47, James Greenhalgh wrote: > On Fri, May 13, 2016 at 04:41:33PM +0200, Christophe Lyon wrote: >> On 13 May 2016 at 16:37, James Greenhalgh wrote: >> > On Wed, May 11, 2016 at 03:23:56PM +0200, Christophe Lyon wrote: >> >> 2016-05-02 Christophe Lyon >> >> >> >> * gcc.target/aarch64/advsimd-intrinsics/vtst.c: Add tests >> >> for vtst_p8 and vtstq_p8. >> > >> > And vtst_p16 and vtstq_p16 too please. >> > >> > vtst_s64 >> > vtstq_s64 >> > vtst_u64 >> > vtstq_u64 are also missing (AArch64 only). >> > >> vtst_p16/vtstq_p16 are AArch64 only too, right? > > Not in my copy of: > > http://infocenter.arm.com/help/topic/com.arm.doc.ihi0073a/IHI0073A_arm_neon_intrinsics_ref.pdf > > I see it is missing from config/arm/arm_neon.h so that's a bug in the GCC > implementation. It should be easy to resolve, map it to the same place > as vtst_u16 and vtst_s16 - this is just a bit operation which takes no > semantics from the data-type. > Maybe you have a way of automatically checking that the doc and arm_neon.h contents match? I mean: - are there other intrinsics documented, but not defined in arm_neon.h ? - are there intrinsics in arm_neon.h, but not in the doc? > Would you mind spinning the fix for that and committing it before this > patch? > I've attached an updated patch which contains the definition for the missing vtst_p16 and vtstq_p16, as well as tests for vtst_p8, vtstq_p8, vtst_p16 and vtstq_p16. >> My introduction message was not clear enough: this series >> only attempts to fully cover AArch32 intrinsics. > > Understood, sorry for the extra noise. > Coverage of AArch64 intrinsics will require another effort :) > Thanks, > James > > 2016-05-19 Christophe Lyon gcc/ * config/arm/arm_neon.h (vtst_p16, vtstq_p16): New. gcc/testsuite/ * gcc.target/aarch64/advsimd-intrinsics/vtst.c: Add tests for vtst_p8, vtstq_p8, vtst_p16 and vtstq_p16. diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h index 07503d7..7997cb4 100644 --- a/gcc/config/arm/arm_neon.h +++ b/gcc/config/arm/arm_neon.h @@ -2607,6 +2607,12 @@ vtst_p8 (poly8x8_t __a, poly8x8_t __b) return (uint8x8_t)__builtin_neon_vtstv8qi ((int8x8_t) __a, (int8x8_t) __b); } +__extension__ static __inline uint16x4_t __attribute__ ((__always_inline__)) +vtst_p16 (poly16x4_t __a, poly16x4_t __b) +{ + return (uint16x4_t)__builtin_neon_vtstv4hi ((int16x4_t) __a, (int16x4_t) __b); +} + __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__)) vtstq_s8 (int8x16_t __a, int8x16_t __b) { @@ -2649,6 +2655,12 @@ vtstq_p8 (poly8x16_t __a, poly8x16_t __b) return (uint8x16_t)__builtin_neon_vtstv16qi ((int8x16_t) __a, (int8x16_t) __b); } +__extension__ static __inline uint16x8_t __attribute__ ((__always_inline__)) +vtstq_p16 (poly16x8_t __a, poly16x8_t __b) +{ + return (uint16x8_t)__builtin_neon_vtstv8hi ((int16x8_t) __a, (int16x8_t) __b); +} + __extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) vabd_s8 (int8x8_t __a, int8x8_t __b) { diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c index 9e74ffb..8f9e651 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vtst.c @@ -32,6 +32,19 @@ VECT_VAR_DECL(expected_unsigned,uint,16,8) [] = { 0x0, 0xffff, VECT_VAR_DECL(expected_unsigned,uint,32,4) [] = { 0x0, 0xffffffff, 0x0, 0xffffffff }; +/* Expected results with poly input. */ +VECT_VAR_DECL(expected_poly,uint,8,8) [] = { 0x0, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff }; +VECT_VAR_DECL(expected_poly,uint,8,16) [] = { 0x0, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff }; +VECT_VAR_DECL(expected_poly,uint,16,4) [] = { 0x0, 0xffff, 0x0, 0xffff }; +VECT_VAR_DECL(expected_poly,uint,16,8) [] = { 0x0, 0xffff, + 0x0, 0xffff, + 0xffff, 0xffff, + 0xffff, 0xffff }; + #define INSN_NAME vtst #define TEST_MSG "VTST/VTSTQ" @@ -71,12 +84,16 @@ FNNAME (INSN_NAME) VDUP(vector2, , uint, u, 8, 8, 15); VDUP(vector2, , uint, u, 16, 4, 5); VDUP(vector2, , uint, u, 32, 2, 1); + VDUP(vector2, , poly, p, 8, 8, 15); + VDUP(vector2, , poly, p, 16, 4, 5); VDUP(vector2, q, int, s, 8, 16, 15); VDUP(vector2, q, int, s, 16, 8, 5); VDUP(vector2, q, int, s, 32, 4, 1); VDUP(vector2, q, uint, u, 8, 16, 15); VDUP(vector2, q, uint, u, 16, 8, 5); VDUP(vector2, q, uint, u, 32, 4, 1); + VDUP(vector2, q, poly, p, 8, 16, 15); + VDUP(vector2, q, poly, p, 16, 8, 5); #define TEST_MACRO_NO64BIT_VARIANT_1_5(MACRO, VAR, T1, T2) \ MACRO(VAR, , T1, T2, 8, 8); \ @@ -109,6 +126,18 @@ FNNAME (INSN_NAME) CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_unsigned, CMT); CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_unsigned, CMT); CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected_unsigned, CMT); + + /* Now, test the variants with poly8 and poly16 as input. */ +#undef CMT +#define CMT " (poly input)" + TEST_BINARY_OP(INSN_NAME, , poly, p, 8, 8); + TEST_BINARY_OP(INSN_NAME, , poly, p, 16, 4); + TEST_BINARY_OP(INSN_NAME, q, poly, p, 8, 16); + TEST_BINARY_OP(INSN_NAME, q, poly, p, 16, 8); + CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected_poly, CMT); + CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected_poly, CMT); + CHECK(TEST_MSG, uint, 8, 16, PRIx8, expected_poly, CMT); + CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected_poly, CMT); } int main (void)