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[209.132.180.131]) by mx.google.com with ESMTPS id n7si212943pdj.247.2015.01.20.07.32.33 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 20 Jan 2015 07:32:34 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-390014-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 22573 invoked by alias); 20 Jan 2015 15:32:18 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 22537 invoked by uid 89); 20 Jan 2015 15:32:16 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-qa0-f46.google.com Received: from mail-qa0-f46.google.com (HELO mail-qa0-f46.google.com) (209.85.216.46) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Tue, 20 Jan 2015 15:32:14 +0000 Received: by mail-qa0-f46.google.com with SMTP id j7so28468371qaq.5 for ; Tue, 20 Jan 2015 07:32:12 -0800 (PST) MIME-Version: 1.0 X-Received: by 10.140.92.33 with SMTP id a30mr29482313qge.30.1421767932095; Tue, 20 Jan 2015 07:32:12 -0800 (PST) Received: by 10.140.84.176 with HTTP; Tue, 20 Jan 2015 07:32:11 -0800 (PST) In-Reply-To: <54B9553A.6060808@arm.com> References: <1421162314-25779-1-git-send-email-christophe.lyon@linaro.org> <1421162314-25779-22-git-send-email-christophe.lyon@linaro.org> <54B9553A.6060808@arm.com> Date: Tue, 20 Jan 2015 16:32:11 +0100 Message-ID: Subject: Re: [[ARM/AArch64][testsuite] 21/36] Add vmovl tests. From: Christophe Lyon To: Tejas Belagod Cc: "gcc-patches@gcc.gnu.org" X-IsSubscribed: yes X-Original-Sender: christophe.lyon@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c04::232 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 On 16 January 2015 at 19:15, Tejas Belagod wrote: > On 13/01/15 15:18, Christophe Lyon wrote: >> >> * gcc.target/aarch64/advsimd-intrinsics/vmovl.c: New file. >> >> diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovl.c >> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovl.c >> new file mode 100644 >> index 0000000..427c9ba >> --- /dev/null >> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovl.c >> @@ -0,0 +1,77 @@ >> +#include >> +#include "arm-neon-ref.h" >> +#include "compute-ref-data.h" >> + >> +/* Expected results. */ >> +VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33, >> + 0x33, 0x33, 0x33, 0x33 }; >> +VECT_VAR_DECL(expected,int,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; >> +VECT_VAR_DECL(expected,int,32,2) [] = { 0x33333333, 0x33333333 }; >> +VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 }; >> +VECT_VAR_DECL(expected,uint,8,8) [] = { 0x33, 0x33, 0x33, 0x33, >> + 0x33, 0x33, 0x33, 0x33 }; >> +VECT_VAR_DECL(expected,uint,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 >> }; >> +VECT_VAR_DECL(expected,uint,32,2) [] = { 0x33333333, 0x33333333 }; >> +VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 }; >> +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, >> + 0x33, 0x33, 0x33, 0x33 }; >> +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 >> }; >> +VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; >> +VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, >> + 0x33, 0x33, 0x33, 0x33, >> + 0x33, 0x33, 0x33, 0x33, >> + 0x33, 0x33, 0x33, 0x33 }; >> +VECT_VAR_DECL(expected,int,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3, >> + 0xfff4, 0xfff5, 0xfff6, 0xfff7 }; >> +VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffff0, 0xfffffff1, >> + 0xfffffff2, 0xfffffff3 }; >> +VECT_VAR_DECL(expected,int,64,2) [] = { 0xfffffffffffffff0, >> + 0xfffffffffffffff1 }; >> +VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, >> + 0x33, 0x33, 0x33, 0x33, >> + 0x33, 0x33, 0x33, 0x33, >> + 0x33, 0x33, 0x33, 0x33 }; >> +VECT_VAR_DECL(expected,uint,16,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, >> + 0xf4, 0xf5, 0xf6, 0xf7 }; >> +VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 >> }; >> +VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffff0, 0xfffffff1 }; >> +VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, >> + 0x33, 0x33, 0x33, 0x33, >> + 0x33, 0x33, 0x33, 0x33, >> + 0x33, 0x33, 0x33, 0x33 }; >> +VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, >> + 0x3333, 0x3333, 0x3333, 0x3333 }; >> +VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, >> + 0x33333333, 0x33333333 }; >> + > > > No poly or float for vmovl. > Here is a new version, with more cleanup: only 16x8, 32x4 and 64x2 variants are necessary. > Otherwise, LGTM. > > Tejas. > > >From 2f56acd54cee2d9b9b62de9e624fb2a64f114101 Mon Sep 17 00:00:00 2001 From: Christophe Lyon Date: Wed, 10 Dec 2014 17:24:48 +0100 Subject: [[ARM/AArch64][testsuite] 21/36] Add vmovl tests. diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovl.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovl.c new file mode 100644 index 0000000..fd94d72 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovl.c @@ -0,0 +1,52 @@ +#include +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +/* Expected results. */ +VECT_VAR_DECL(expected,int,16,8) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3, + 0xfff4, 0xfff5, 0xfff6, 0xfff7 }; +VECT_VAR_DECL(expected,int,32,4) [] = { 0xfffffff0, 0xfffffff1, + 0xfffffff2, 0xfffffff3 }; +VECT_VAR_DECL(expected,int,64,2) [] = { 0xfffffffffffffff0, + 0xfffffffffffffff1 }; +VECT_VAR_DECL(expected,uint,16,8) [] = { 0xf0, 0xf1, 0xf2, 0xf3, + 0xf4, 0xf5, 0xf6, 0xf7 }; +VECT_VAR_DECL(expected,uint,32,4) [] = { 0xfff0, 0xfff1, 0xfff2, 0xfff3 }; +VECT_VAR_DECL(expected,uint,64,2) [] = { 0xfffffff0, 0xfffffff1 }; + +#define TEST_MSG "VMOVL" +void exec_vmovl (void) +{ + /* Basic test: vec128=vmovl(vec64), then store the result. */ +#define TEST_VMOVL(T1, T2, W, W2, N) \ + VECT_VAR(vector128, T1, W2, N) = \ + vmovl_##T2##W(VECT_VAR(vector64, T1, W, N)); \ + vst1q_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector128, T1, W2, N)) + + DECL_VARIABLE_64BITS_VARIANTS(vector64); + DECL_VARIABLE_128BITS_VARIANTS(vector128); + + TEST_MACRO_64BITS_VARIANTS_2_5(VLOAD, vector64, buffer); + + clean_results (); + + TEST_VMOVL(int, s, 8, 16, 8); + TEST_VMOVL(int, s, 16, 32, 4); + TEST_VMOVL(int, s, 32, 64, 2); + TEST_VMOVL(uint, u, 8, 16, 8); + TEST_VMOVL(uint, u, 16, 32, 4); + TEST_VMOVL(uint, u, 32, 64, 2); + + CHECK(TEST_MSG, int, 16, 8, PRIx16, expected, ""); + CHECK(TEST_MSG, int, 32, 4, PRIx32, expected, ""); + CHECK(TEST_MSG, int, 64, 2, PRIx64, expected, ""); + CHECK(TEST_MSG, uint, 16, 8, PRIx16, expected, ""); + CHECK(TEST_MSG, uint, 32, 4, PRIx32, expected, ""); + CHECK(TEST_MSG, uint, 64, 2, PRIx64, expected, ""); +} + +int main (void) +{ + exec_vmovl (); + return 0; +} -- 2.1.0