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[209.132.180.131]) by mx.google.com with ESMTPS id j66si2909390ioi.123.2015.10.13.06.05.17 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 13 Oct 2015 06:05:18 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-410021-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 14525 invoked by alias); 13 Oct 2015 13:05:06 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 14508 invoked by uid 89); 13 Oct 2015 13:05:05 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-qk0-f182.google.com Received: from mail-qk0-f182.google.com (HELO mail-qk0-f182.google.com) (209.85.220.182) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Tue, 13 Oct 2015 13:05:04 +0000 Received: by qkht68 with SMTP id t68so6509045qkh.3 for ; Tue, 13 Oct 2015 06:05:02 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.55.42.73 with SMTP id q70mr40028606qkh.22.1444741501922; Tue, 13 Oct 2015 06:05:01 -0700 (PDT) Received: by 10.140.44.10 with HTTP; Tue, 13 Oct 2015 06:05:01 -0700 (PDT) In-Reply-To: <20151012132854.GA32787@arm.com> References: <20151007150941.GA31205@arm.com> <20151008091230.GA13098@arm.com> <20151012132854.GA32787@arm.com> Date: Tue, 13 Oct 2015 15:05:01 +0200 Message-ID: Subject: Re: [AArch64_be] Fix vtbl[34] and vtbx4 From: Christophe Lyon To: James Greenhalgh Cc: "gcc-patches@gcc.gnu.org" X-IsSubscribed: yes X-Original-Sender: christophe.lyon@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c04::230 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 On 12 October 2015 at 15:30, James Greenhalgh wrote: > On Fri, Oct 09, 2015 at 05:16:05PM +0100, Christophe Lyon wrote: >> On 8 October 2015 at 11:12, James Greenhalgh wrote: >> > On Wed, Oct 07, 2015 at 09:07:30PM +0100, Christophe Lyon wrote: >> >> On 7 October 2015 at 17:09, James Greenhalgh wrote: >> >> > On Tue, Sep 15, 2015 at 05:25:25PM +0100, Christophe Lyon wrote: >> >> > >> >> > Why do we want this for vtbx4 rather than putting out a VTBX instruction >> >> > directly (as in the inline asm versions you replace)? >> >> > >> >> I just followed the pattern used for vtbx3. >> >> >> >> > This sequence does make sense for vtbx3. >> >> In fact, I don't see why vtbx3 and vtbx4 should be different? >> > >> > The difference between TBL and TBX is in their handling of a request to >> > select an out-of-range value. For TBL this returns zero, for TBX this >> > returns the value which was already in the destination register. >> > >> > Because the byte-vectors used by the TBX instruction in aarch64 are 128-bit >> > (so two of them togather allow selecting elements in the range 0-31), and >> > vtbx3 needs to emulate the AArch32 behaviour of picking elements from 3x64-bit >> > vectors (allowing elements in the range 0-23), we need to manually check for >> > values which would have been out-of-range on AArch32, but are not out >> > of range for AArch64 and handle them appropriately. For vtbx4 on the other >> > hand, 2x128-bit registers give the range 0..31 and 4x64-bit registers give >> > the range 0..31, so we don't need the special masked handling. >> > >> > You can find the suggested instruction sequences for the Neon intrinsics >> > in this document: >> > >> > http://infocenter.arm.com/help/topic/com.arm.doc.ihi0073a/IHI0073A_arm_neon_intrinsics_ref.pdf >> > >> >> Hi James, >> >> Please find attached an updated version which hopefully addresses your comments. >> Tested on aarch64-none-elf and aarch64_be-none-elf using the Foundation Model. >> >> OK? > > Looks good to me, > > Thanks, > James > I commited this as r228716, and noticed later that gcc.target/aarch64/table-intrinsics.c failed because of this patch. This is because that testcase scans the assembly for 'tbl v' or 'tbx v', but since I replaced some asm statements, the space is now a tab. I plan to commit this (probably obvious?): 2015-10-13 Christophe Lyon * gcc/testsuite/gcc.target/aarch64/table-intrinsics.c: Fix regexp after r228716 (Fix vtbl[34] and vtbx4). Index: gcc/testsuite/gcc.target/aarch64/table-intrinsics.c =================================================================== --- gcc/testsuite/gcc.target/aarch64/table-intrinsics.c (revision 228759) +++ gcc/testsuite/gcc.target/aarch64/table-intrinsics.c (working copy) @@ -435,5 +435,5 @@ return vqtbx4q_p8 (r, tab, idx); } -/* { dg-final { scan-assembler-times "tbl v" 42} } */ -/* { dg-final { scan-assembler-times "tbx v" 30} } */ +/* { dg-final { scan-assembler-times "tbl\[ |\t\]*v" 42} } */ +/* { dg-final { scan-assembler-times "tbx\[ |\t\]*v" 30} } */