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[209.132.180.131]) by mx.google.com with ESMTPS id rw7si2012846pac.15.2015.08.04.06.26.26 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Aug 2015 06:26:27 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-404648-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 47756 invoked by alias); 4 Aug 2015 13:26:15 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 47742 invoked by uid 89); 4 Aug 2015 13:26:14 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-qk0-f175.google.com Received: from mail-qk0-f175.google.com (HELO mail-qk0-f175.google.com) (209.85.220.175) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Tue, 04 Aug 2015 13:26:12 +0000 Received: by qkdv3 with SMTP id v3so2994487qkd.3 for ; Tue, 04 Aug 2015 06:26:10 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.55.19.136 with SMTP id 8mr6268013qkt.103.1438694769953; Tue, 04 Aug 2015 06:26:09 -0700 (PDT) Received: by 10.140.96.181 with HTTP; Tue, 4 Aug 2015 06:26:09 -0700 (PDT) In-Reply-To: References: <1437033404-4759-1-git-send-email-christophe.lyon@linaro.org> <55AE50B5.1040507@arm.com> Date: Tue, 4 Aug 2015 15:26:09 +0200 Message-ID: Subject: Re: [ARM] Fix vget_lane for big-endian targets From: Christophe Lyon To: Kyrill Tkachov Cc: "gcc-patches@gcc.gnu.org" X-IsSubscribed: yes X-Original-Sender: christophe.lyon@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c04::234 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 On 4 August 2015 at 14:09, Christophe Lyon wrote: > On 21 July 2015 at 16:01, Kyrill Tkachov wrote: >> >> On 16/07/15 08:56, Christophe Lyon wrote: >>> >>> AdvSIMD vget_lane tests currently fail on armeb targets when dealing >>> with vectors of 2 64-bits elements. This patches fixes it, by adding a >>> code fragment similar to what is dones in other cases. I could have >>> simplified it a bit given that the vector width is known, but I chose >>> to hardcode 'reg_nelts = 2' to keep the code closer to what is done >>> elsewhere. >>> >>> OK for trunk? >>> >>> Christophe >>> >>> 2015-07-16 Christophe Lyon >>> >>> * config/arm/neon.md (neon_vget_lanev2di): Handle big-endian >>> targets. >> >> >> I see we do this for other lanewise patterns as well. >> Has this been tested on an arm big-endian target? >> >> If so, ok for trunk. > > I forgot to mention that yes, I actually tested it on arm big-endian, > using QEMU. > Since Alan committed his patch, there was a conflict with mine. Here is what I committed, the change being obvious enough IMO. (I did re-run make check on armeb using qemu) Christophe > Christophe. > >> >> Thanks, >> Kyrill >> >> >>> >>> diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md >>> index 654d9d5..59ddc5b 100644 >>> --- a/gcc/config/arm/neon.md >>> +++ b/gcc/config/arm/neon.md >>> @@ -2736,6 +2736,19 @@ >>> (match_operand:SI 2 "immediate_operand" "")] >>> "TARGET_NEON" >>> { >>> + if (BYTES_BIG_ENDIAN) >>> + { >>> + /* The intrinsics are defined in terms of a model where the >>> + element ordering in memory is vldm order, whereas the generic >>> + RTL is defined in terms of a model where the element ordering >>> + in memory is array order. Convert the lane number to conform >>> + to this model. */ >>> + unsigned int elt = INTVAL (operands[2]); >>> + unsigned int reg_nelts = 2; >>> + elt ^= reg_nelts - 1; >>> + operands[2] = GEN_INT (elt); >>> + } >>> + >>> switch (INTVAL (operands[2])) >>> { >>> case 0: >> >> 2015-08-04 Christophe Lyon * config/arm/neon.md (neon_vget_lanev2di): Handle big-endian targets. diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 4af74ce..b1bf26a 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -2731,7 +2731,22 @@ (match_operand:SI 2 "immediate_operand" "")] "TARGET_NEON" { - int lane = INTVAL (operands[2]); + int lane; + +if (BYTES_BIG_ENDIAN) + { + /* The intrinsics are defined in terms of a model where the + element ordering in memory is vldm order, whereas the generic + RTL is defined in terms of a model where the element ordering + in memory is array order. Convert the lane number to conform + to this model. */ + unsigned int elt = INTVAL (operands[2]); + unsigned int reg_nelts = 2; + elt ^= reg_nelts - 1; + operands[2] = GEN_INT (elt); + } + + lane = INTVAL (operands[2]); gcc_assert ((lane ==0) || (lane == 1)); emit_move_insn (operands[0], lane == 0 ? gen_lowpart (DImode, operands[1])