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[209.132.180.131]) by mx.google.com with ESMTPS id p186si21656977pfg.235.2016.06.21.01.46.12 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 21 Jun 2016 01:46:13 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-430201-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-430201-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-430201-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; q= dns; s=default; b=WiE0BL1GJO34Sxy1XZGSDgi9/pfTRMj4FT8LMRgaka4YpC o21C6jOsHZzWRLl+6JuW42KnzgBT2egXhaBtTeXIpHIiKXiE2vKGWswOyf1ltmZ9 rLuk6IRPkhrzsKZu1lxiUVjHCrnjDID5crt4FXjritv0w6yDn8Kn0XObRJSYw= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; s= default; bh=xmzz6nmVRHNMDzZ3qQEoQFi2E1k=; b=fwuRbr49JnoWNJx+RP6S sXzRlx97ihwPRKgO+IvLbQLYPGGjQo6ohzt9KGWaZRGYI7AXE3jNKr+EUmADcIIa VOqGTwrPUtIhZZ81sMmRqaeRysHfbtgS72X7eiZcm8QNS9n80vv8s1PD9hqjDIR1 8/F1hyxTIbRoltA+iAnSBu0= Received: (qmail 6559 invoked by alias); 21 Jun 2016 08:45:58 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 6531 invoked by uid 89); 21 Jun 2016 08:45:56 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.1 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 spammy=christophelyonlinaroorg, christophe.lyon@linaro.org, sk:check_e, lawrence X-HELO: mail-qk0-f169.google.com Received: from mail-qk0-f169.google.com (HELO mail-qk0-f169.google.com) (209.85.220.169) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Tue, 21 Jun 2016 08:45:45 +0000 Received: by mail-qk0-f169.google.com with SMTP id a186so11532885qkf.0 for ; Tue, 21 Jun 2016 01:45:45 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=kFT+m5sfLkZeqalY57UNcX8Kei+ti+DR5dHfbyo1alY=; b=l81CTbs5SZrdlmL42hCQrLCK/jnh0USw5pBjApf+RUYrjwVdrbfjZ01jYaYFOcPc/f SYq0Lo+FYbFsyDy4dAk/DpDPbh2DlxsZbiZlyrK4IdYRRm4oxGIsKJV/1nYQEy1QDjKl r2Vz6Yi4gpkqBNB50ACtvaz6MlGLYeK2/h+1oswNThPVgGNgNUJTNfgsCMpMcMKugmtg xZKP2YP2gvhNaOi2lqpX2g/VpTuhlXiLV/NyNzc3xsq8UDrCN1/5kMtJDO5TiBBsBlOw EJsacDKQHXKHOe7XiahUf/+hsb+av413uvUfbM0h9eC+rVs/tMIpoXBeinfLanMRX8u7 /rgw== X-Gm-Message-State: ALyK8tLeSl4uZF3km0UGgINnkbEbyr/uRAjXBUIfzVHgWg8KAZ9/yDVBr53mZZ8WDguDfa0k/Up3tomksfAg0zkk X-Received: by 10.237.37.99 with SMTP id w32mr27621404qtc.95.1466498743468; Tue, 21 Jun 2016 01:45:43 -0700 (PDT) MIME-Version: 1.0 Received: by 10.140.99.78 with HTTP; Tue, 21 Jun 2016 01:45:42 -0700 (PDT) From: Christophe Lyon Date: Tue, 21 Jun 2016 10:45:42 +0200 Message-ID: Subject: [ARM][testsuite] Add missing guards to fp16 AdvSIMD tests To: "gcc-patches@gcc.gnu.org" X-IsSubscribed: yes Hi, I've noticed that some guards were missing on some of the AdvSIMD tests involving fp16 code. The attached patch fixes, although I didn't notice any difference in validation: I have no configuration where check_effective_target_arm_neon_fp16_ok fails. I did locally modify this effective target to always return false to make sure I covered all the missing guards. However, I'm not sure when check_effective_target_arm_neon_fp16_ok can fail? This effective target test was added by Alan Lawrence a few months ago. OK? Christophe gcc/testsuite/ChangeLog: 2016-06-21 Christophe Lyon * gcc.target/aarch64/advsimd-intrinsics/vget_lane.c: Add ifdef around fp16 code. * gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f16_indices_1.c: Add arm_neon_fp16_ok effective target. * gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f16_indices_1.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f16_indices_1.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f16_indices_1.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f16_indices_1.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f16_indices_1.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f16_indices_1.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f16_indices_1.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f16_indices_1.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f16_indices_1.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f16_indices_1.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f16_indices_1.c: Likewise. diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_lane.c index fe41c5f..ee6d650 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_lane.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vget_lane.c @@ -54,10 +54,12 @@ void exec_vget_lane (void) uint32_t var_int32; float32_t var_float32; } var_int32_float32; +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) union { uint16_t var_int16; float16_t var_float16; } var_int16_float16; +#endif #define TEST_VGET_LANE_FP(Q, T1, T2, W, N, L) \ VAR(var, T1, W) = vget##Q##_lane_##T2##W(VECT_VAR(vector, T1, W, N), L); \ diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c index 0de2ab3..127e1aa 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret.c @@ -665,9 +665,11 @@ void exec_vreinterpret (void) /* Initialize input "vector" from "buffer". */ TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vector, buffer); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) VLOAD(vector, buffer, , float, f, 16, 4); - VLOAD(vector, buffer, , float, f, 32, 2); VLOAD(vector, buffer, q, float, f, 16, 8); +#endif + VLOAD(vector, buffer, , float, f, 32, 2); VLOAD(vector, buffer, q, float, f, 32, 4); /* vreinterpret_s8_xx. */ @@ -680,7 +682,9 @@ void exec_vreinterpret (void) TEST_VREINTERPRET(, int, s, 8, 8, uint, u, 64, 1, expected_s8_7); TEST_VREINTERPRET(, int, s, 8, 8, poly, p, 8, 8, expected_s8_8); TEST_VREINTERPRET(, int, s, 8, 8, poly, p, 16, 4, expected_s8_9); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) TEST_VREINTERPRET(, int, s, 8, 8, float, f, 16, 4, expected_s8_10); +#endif /* vreinterpret_s16_xx. */ TEST_VREINTERPRET(, int, s, 16, 4, int, s, 8, 8, expected_s16_1); @@ -692,7 +696,9 @@ void exec_vreinterpret (void) TEST_VREINTERPRET(, int, s, 16, 4, uint, u, 64, 1, expected_s16_7); TEST_VREINTERPRET(, int, s, 16, 4, poly, p, 8, 8, expected_s16_8); TEST_VREINTERPRET(, int, s, 16, 4, poly, p, 16, 4, expected_s16_9); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) TEST_VREINTERPRET(, int, s, 16, 4, float, f, 16, 4, expected_s16_10); +#endif /* vreinterpret_s32_xx. */ TEST_VREINTERPRET(, int, s, 32, 2, int, s, 8, 8, expected_s32_1); @@ -704,7 +710,9 @@ void exec_vreinterpret (void) TEST_VREINTERPRET(, int, s, 32, 2, uint, u, 64, 1, expected_s32_7); TEST_VREINTERPRET(, int, s, 32, 2, poly, p, 8, 8, expected_s32_8); TEST_VREINTERPRET(, int, s, 32, 2, poly, p, 16, 4, expected_s32_9); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) TEST_VREINTERPRET(, int, s, 32, 2, float, f, 16, 4, expected_s32_10); +#endif /* vreinterpret_s64_xx. */ TEST_VREINTERPRET(, int, s, 64, 1, int, s, 8, 8, expected_s64_1); @@ -716,7 +724,9 @@ void exec_vreinterpret (void) TEST_VREINTERPRET(, int, s, 64, 1, uint, u, 64, 1, expected_s64_7); TEST_VREINTERPRET(, int, s, 64, 1, poly, p, 8, 8, expected_s64_8); TEST_VREINTERPRET(, int, s, 64, 1, poly, p, 16, 4, expected_s64_9); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) TEST_VREINTERPRET(, int, s, 64, 1, float, f, 16, 4, expected_s64_10); +#endif /* vreinterpret_u8_xx. */ TEST_VREINTERPRET(, uint, u, 8, 8, int, s, 8, 8, expected_u8_1); @@ -728,7 +738,9 @@ void exec_vreinterpret (void) TEST_VREINTERPRET(, uint, u, 8, 8, uint, u, 64, 1, expected_u8_7); TEST_VREINTERPRET(, uint, u, 8, 8, poly, p, 8, 8, expected_u8_8); TEST_VREINTERPRET(, uint, u, 8, 8, poly, p, 16, 4, expected_u8_9); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) TEST_VREINTERPRET(, uint, u, 8, 8, float, f, 16, 4, expected_u8_10); +#endif /* vreinterpret_u16_xx. */ TEST_VREINTERPRET(, uint, u, 16, 4, int, s, 8, 8, expected_u16_1); @@ -740,7 +752,9 @@ void exec_vreinterpret (void) TEST_VREINTERPRET(, uint, u, 16, 4, uint, u, 64, 1, expected_u16_7); TEST_VREINTERPRET(, uint, u, 16, 4, poly, p, 8, 8, expected_u16_8); TEST_VREINTERPRET(, uint, u, 16, 4, poly, p, 16, 4, expected_u16_9); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) TEST_VREINTERPRET(, uint, u, 16, 4, float, f, 16, 4, expected_u16_10); +#endif /* vreinterpret_u32_xx. */ TEST_VREINTERPRET(, uint, u, 32, 2, int, s, 8, 8, expected_u32_1); @@ -752,7 +766,9 @@ void exec_vreinterpret (void) TEST_VREINTERPRET(, uint, u, 32, 2, uint, u, 64, 1, expected_u32_7); TEST_VREINTERPRET(, uint, u, 32, 2, poly, p, 8, 8, expected_u32_8); TEST_VREINTERPRET(, uint, u, 32, 2, poly, p, 16, 4, expected_u32_9); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) TEST_VREINTERPRET(, uint, u, 32, 2, float, f, 16, 4, expected_u32_10); +#endif /* vreinterpret_u64_xx. */ TEST_VREINTERPRET(, uint, u, 64, 1, int, s, 8, 8, expected_u64_1); @@ -764,7 +780,9 @@ void exec_vreinterpret (void) TEST_VREINTERPRET(, uint, u, 64, 1, uint, u, 32, 2, expected_u64_7); TEST_VREINTERPRET(, uint, u, 64, 1, poly, p, 8, 8, expected_u64_8); TEST_VREINTERPRET(, uint, u, 64, 1, poly, p, 16, 4, expected_u64_9); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) TEST_VREINTERPRET(, uint, u, 64, 1, float, f, 16, 4, expected_u64_10); +#endif /* vreinterpret_p8_xx. */ TEST_VREINTERPRET_POLY(, poly, p, 8, 8, int, s, 8, 8, expected_p8_1); @@ -776,7 +794,9 @@ void exec_vreinterpret (void) TEST_VREINTERPRET_POLY(, poly, p, 8, 8, uint, u, 32, 2, expected_p8_7); TEST_VREINTERPRET_POLY(, poly, p, 8, 8, uint, u, 64, 1, expected_p8_8); TEST_VREINTERPRET_POLY(, poly, p, 8, 8, poly, p, 16, 4, expected_p8_9); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) TEST_VREINTERPRET_POLY(, poly, p, 8, 8, float, f, 16, 4, expected_p8_10); +#endif /* vreinterpret_p16_xx. */ TEST_VREINTERPRET_POLY(, poly, p, 16, 4, int, s, 8, 8, expected_p16_1); @@ -788,7 +808,9 @@ void exec_vreinterpret (void) TEST_VREINTERPRET_POLY(, poly, p, 16, 4, uint, u, 32, 2, expected_p16_7); TEST_VREINTERPRET_POLY(, poly, p, 16, 4, uint, u, 64, 1, expected_p16_8); TEST_VREINTERPRET_POLY(, poly, p, 16, 4, poly, p, 8, 8, expected_p16_9); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) TEST_VREINTERPRET_POLY(, poly, p, 16, 4, float, f, 16, 4, expected_p16_10); +#endif /* vreinterpretq_s8_xx. */ TEST_VREINTERPRET(q, int, s, 8, 16, int, s, 16, 8, expected_q_s8_1); @@ -800,7 +822,9 @@ void exec_vreinterpret (void) TEST_VREINTERPRET(q, int, s, 8, 16, uint, u, 64, 2, expected_q_s8_7); TEST_VREINTERPRET(q, int, s, 8, 16, poly, p, 8, 16, expected_q_s8_8); TEST_VREINTERPRET(q, int, s, 8, 16, poly, p, 16, 8, expected_q_s8_9); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) TEST_VREINTERPRET(q, int, s, 8, 16, float, f, 16, 8, expected_q_s8_10); +#endif /* vreinterpretq_s16_xx. */ TEST_VREINTERPRET(q, int, s, 16, 8, int, s, 8, 16, expected_q_s16_1); @@ -812,7 +836,9 @@ void exec_vreinterpret (void) TEST_VREINTERPRET(q, int, s, 16, 8, uint, u, 64, 2, expected_q_s16_7); TEST_VREINTERPRET(q, int, s, 16, 8, poly, p, 8, 16, expected_q_s16_8); TEST_VREINTERPRET(q, int, s, 16, 8, poly, p, 16, 8, expected_q_s16_9); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) TEST_VREINTERPRET(q, int, s, 16, 8, float, f, 16, 8, expected_q_s16_10); +#endif /* vreinterpretq_s32_xx. */ TEST_VREINTERPRET(q, int, s, 32, 4, int, s, 8, 16, expected_q_s32_1); @@ -824,7 +850,9 @@ void exec_vreinterpret (void) TEST_VREINTERPRET(q, int, s, 32, 4, uint, u, 64, 2, expected_q_s32_7); TEST_VREINTERPRET(q, int, s, 32, 4, poly, p, 8, 16, expected_q_s32_8); TEST_VREINTERPRET(q, int, s, 32, 4, poly, p, 16, 8, expected_q_s32_9); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) TEST_VREINTERPRET(q, int, s, 32, 4, float, f, 16, 8, expected_q_s32_10); +#endif /* vreinterpretq_s64_xx. */ TEST_VREINTERPRET(q, int, s, 64, 2, int, s, 8, 16, expected_q_s64_1); @@ -836,7 +864,9 @@ void exec_vreinterpret (void) TEST_VREINTERPRET(q, int, s, 64, 2, uint, u, 64, 2, expected_q_s64_7); TEST_VREINTERPRET(q, int, s, 64, 2, poly, p, 8, 16, expected_q_s64_8); TEST_VREINTERPRET(q, int, s, 64, 2, poly, p, 16, 8, expected_q_s64_9); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) TEST_VREINTERPRET(q, int, s, 64, 2, float, f, 16, 8, expected_q_s64_10); +#endif /* vreinterpretq_u8_xx. */ TEST_VREINTERPRET(q, uint, u, 8, 16, int, s, 8, 16, expected_q_u8_1); @@ -848,7 +878,9 @@ void exec_vreinterpret (void) TEST_VREINTERPRET(q, uint, u, 8, 16, uint, u, 64, 2, expected_q_u8_7); TEST_VREINTERPRET(q, uint, u, 8, 16, poly, p, 8, 16, expected_q_u8_8); TEST_VREINTERPRET(q, uint, u, 8, 16, poly, p, 16, 8, expected_q_u8_9); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) TEST_VREINTERPRET(q, uint, u, 8, 16, float, f, 16, 8, expected_q_u8_10); +#endif /* vreinterpretq_u16_xx. */ TEST_VREINTERPRET(q, uint, u, 16, 8, int, s, 8, 16, expected_q_u16_1); @@ -860,7 +892,9 @@ void exec_vreinterpret (void) TEST_VREINTERPRET(q, uint, u, 16, 8, uint, u, 64, 2, expected_q_u16_7); TEST_VREINTERPRET(q, uint, u, 16, 8, poly, p, 8, 16, expected_q_u16_8); TEST_VREINTERPRET(q, uint, u, 16, 8, poly, p, 16, 8, expected_q_u16_9); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) TEST_VREINTERPRET(q, uint, u, 16, 8, float, f, 16, 8, expected_q_u16_10); +#endif /* vreinterpretq_u32_xx. */ TEST_VREINTERPRET(q, uint, u, 32, 4, int, s, 8, 16, expected_q_u32_1); @@ -872,7 +906,9 @@ void exec_vreinterpret (void) TEST_VREINTERPRET(q, uint, u, 32, 4, uint, u, 64, 2, expected_q_u32_7); TEST_VREINTERPRET(q, uint, u, 32, 4, poly, p, 8, 16, expected_q_u32_8); TEST_VREINTERPRET(q, uint, u, 32, 4, poly, p, 16, 8, expected_q_u32_9); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) TEST_VREINTERPRET(q, uint, u, 32, 4, float, f, 16, 8, expected_q_u32_10); +#endif /* vreinterpretq_u64_xx. */ TEST_VREINTERPRET(q, uint, u, 64, 2, int, s, 8, 16, expected_q_u64_1); @@ -884,7 +920,9 @@ void exec_vreinterpret (void) TEST_VREINTERPRET(q, uint, u, 64, 2, uint, u, 32, 4, expected_q_u64_7); TEST_VREINTERPRET(q, uint, u, 64, 2, poly, p, 8, 16, expected_q_u64_8); TEST_VREINTERPRET(q, uint, u, 64, 2, poly, p, 16, 8, expected_q_u64_9); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) TEST_VREINTERPRET(q, uint, u, 64, 2, float, f, 16, 8, expected_q_u64_10); +#endif /* vreinterpretq_p8_xx. */ TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, int, s, 8, 16, expected_q_p8_1); @@ -896,7 +934,9 @@ void exec_vreinterpret (void) TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, uint, u, 32, 4, expected_q_p8_7); TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, uint, u, 64, 2, expected_q_p8_8); TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, poly, p, 16, 8, expected_q_p8_9); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, float, f, 16, 8, expected_q_p8_10); +#endif /* vreinterpretq_p16_xx. */ TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, int, s, 8, 16, expected_q_p16_1); @@ -908,7 +948,9 @@ void exec_vreinterpret (void) TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, uint, u, 32, 4, expected_q_p16_7); TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, uint, u, 64, 2, expected_q_p16_8); TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, poly, p, 8, 16, expected_q_p16_9); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, float, f, 16, 8, expected_q_p16_10); +#endif /* vreinterpret_f32_xx. */ TEST_VREINTERPRET_FP(, float, f, 32, 2, int, s, 8, 8, expected_f32_1); @@ -921,7 +963,9 @@ void exec_vreinterpret (void) TEST_VREINTERPRET_FP(, float, f, 32, 2, uint, u, 64, 1, expected_f32_8); TEST_VREINTERPRET_FP(, float, f, 32, 2, poly, p, 8, 8, expected_f32_9); TEST_VREINTERPRET_FP(, float, f, 32, 2, poly, p, 16, 4, expected_f32_10); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) TEST_VREINTERPRET_FP(, float, f, 32, 2, float, f, 16, 4, expected_f32_11); +#endif /* vreinterpretq_f32_xx. */ TEST_VREINTERPRET_FP(q, float, f, 32, 4, int, s, 8, 16, expected_q_f32_1); @@ -934,7 +978,9 @@ void exec_vreinterpret (void) TEST_VREINTERPRET_FP(q, float, f, 32, 4, uint, u, 64, 2, expected_q_f32_8); TEST_VREINTERPRET_FP(q, float, f, 32, 4, poly, p, 8, 16, expected_q_f32_9); TEST_VREINTERPRET_FP(q, float, f, 32, 4, poly, p, 16, 8, expected_q_f32_10); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) TEST_VREINTERPRET_FP(q, float, f, 32, 4, float, f, 16, 8, expected_q_f32_11); +#endif /* vreinterpret_xx_f32. */ TEST_VREINTERPRET(, int, s, 8, 8, float, f, 32, 2, expected_xx_f32_1); @@ -947,7 +993,9 @@ void exec_vreinterpret (void) TEST_VREINTERPRET(, uint, u, 64, 1, float, f, 32, 2, expected_xx_f32_8); TEST_VREINTERPRET_POLY(, poly, p, 8, 8, float, f, 32, 2, expected_xx_f32_9); TEST_VREINTERPRET_POLY(, poly, p, 16, 4, float, f, 32, 2, expected_xx_f32_10); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) TEST_VREINTERPRET_FP(, float, f, 16, 4, float, f, 32, 2, expected_xx_f32_11); +#endif /* vreinterpretq_xx_f32. */ TEST_VREINTERPRET(q, int, s, 8, 16, float, f, 32, 4, expected_q_xx_f32_1); @@ -960,6 +1008,7 @@ void exec_vreinterpret (void) TEST_VREINTERPRET(q, uint, u, 64, 2, float, f, 32, 4, expected_q_xx_f32_8); TEST_VREINTERPRET_POLY(q, poly, p, 8, 16, float, f, 32, 4, expected_q_xx_f32_9); TEST_VREINTERPRET_POLY(q, poly, p, 16, 8, float, f, 32, 4, expected_q_xx_f32_10); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) TEST_VREINTERPRET_FP(q, float, f, 16, 8, float, f, 32, 4, expected_q_xx_f32_11); /* vreinterpret_f16_xx. */ @@ -985,6 +1034,7 @@ void exec_vreinterpret (void) TEST_VREINTERPRET_FP(q, float, f, 16, 8, uint, u, 64, 2, expected_q_f16_8); TEST_VREINTERPRET_FP(q, float, f, 16, 8, poly, p, 8, 16, expected_q_f16_9); TEST_VREINTERPRET_FP(q, float, f, 16, 8, poly, p, 16, 8, expected_q_f16_10); +#endif } int main (void) diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c index 8ba5272..8086415 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c @@ -86,7 +86,9 @@ int main (void) TEST_MACRO_128BITS_VARIANTS_2_5(VLOAD, vreint_vector, buffer); VLOAD(vreint_vector, buffer, q, poly, p, 64, 2); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) VLOAD(vreint_vector, buffer, q, float, f, 16, 8); +#endif VLOAD(vreint_vector, buffer, q, float, f, 32, 4); /* vreinterpretq_p128_* tests. */ @@ -115,7 +117,9 @@ int main (void) TEST_VREINTERPRET128(q, poly, p, 128, 1, uint, u, 64, 2, vreint_expected_q_p128_u64); TEST_VREINTERPRET128(q, poly, p, 128, 1, poly, p, 8, 16, vreint_expected_q_p128_p8); TEST_VREINTERPRET128(q, poly, p, 128, 1, poly, p, 16, 8, vreint_expected_q_p128_p16); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) TEST_VREINTERPRET128(q, poly, p, 128, 1, float, f, 16, 8, vreint_expected_q_p128_f16); +#endif TEST_VREINTERPRET128(q, poly, p, 128, 1, float, f, 32, 4, vreint_expected_q_p128_f32); /* vreinterpretq_*_p128 tests. */ @@ -153,7 +157,9 @@ int main (void) TEST_VREINTERPRET_FROM_P128(q, uint, u, 64, 2, poly, p, 128, 1, vreint_expected_q_u64_p128); TEST_VREINTERPRET_FROM_P128(q, poly, p, 8, 16, poly, p, 128, 1, vreint_expected_q_p8_p128); TEST_VREINTERPRET_FROM_P128(q, poly, p, 16, 8, poly, p, 128, 1, vreint_expected_q_p16_p128); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) TEST_VREINTERPRET_FP_FROM_P128(q, float, f, 16, 8, poly, p, 128, 1, vreint_expected_q_f16_p128); +#endif TEST_VREINTERPRET_FP_FROM_P128(q, float, f, 32, 4, poly, p, 128, 1, vreint_expected_q_f32_p128); return 0; diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c index b000797..1d8cf9a 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p64.c @@ -132,8 +132,10 @@ int main (void) TEST_MACRO_ALL_VARIANTS_2_5(VLOAD, vreint_vector, buffer); VLOAD(vreint_vector, buffer, , poly, p, 64, 1); VLOAD(vreint_vector, buffer, q, poly, p, 64, 2); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) VLOAD(vreint_vector, buffer, , float, f, 16, 4); VLOAD(vreint_vector, buffer, q, float, f, 16, 8); +#endif VLOAD(vreint_vector, buffer, , float, f, 32, 2); VLOAD(vreint_vector, buffer, q, float, f, 32, 4); @@ -150,7 +152,9 @@ int main (void) TEST_VREINTERPRET(, poly, p, 64, 1, uint, u, 64, 1, vreint_expected_p64_u64); TEST_VREINTERPRET(, poly, p, 64, 1, poly, p, 8, 8, vreint_expected_p64_p8); TEST_VREINTERPRET(, poly, p, 64, 1, poly, p, 16, 4, vreint_expected_p64_p16); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) TEST_VREINTERPRET(, poly, p, 64, 1, float, f, 16, 4, vreint_expected_p64_f16); +#endif TEST_VREINTERPRET(, poly, p, 64, 1, float, f, 32, 2, vreint_expected_p64_f32); /* vreinterpretq_p64_* tests. */ @@ -166,7 +170,9 @@ int main (void) TEST_VREINTERPRET(q, poly, p, 64, 2, uint, u, 64, 2, vreint_expected_q_p64_u64); TEST_VREINTERPRET(q, poly, p, 64, 2, poly, p, 8, 16, vreint_expected_q_p64_p8); TEST_VREINTERPRET(q, poly, p, 64, 2, poly, p, 16, 8, vreint_expected_q_p64_p16); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) TEST_VREINTERPRET(q, poly, p, 64, 2, float, f, 16, 8, vreint_expected_q_p64_f16); +#endif TEST_VREINTERPRET(q, poly, p, 64, 2, float, f, 32, 4, vreint_expected_q_p64_f32); /* vreinterpret_*_p64 tests. */ @@ -183,7 +189,9 @@ int main (void) TEST_VREINTERPRET(, uint, u, 64, 1, poly, p, 64, 1, vreint_expected_u64_p64); TEST_VREINTERPRET(, poly, p, 8, 8, poly, p, 64, 1, vreint_expected_p8_p64); TEST_VREINTERPRET(, poly, p, 16, 4, poly, p, 64, 1, vreint_expected_p16_p64); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) TEST_VREINTERPRET_FP(, float, f, 16, 4, poly, p, 64, 1, vreint_expected_f16_p64); +#endif TEST_VREINTERPRET_FP(, float, f, 32, 2, poly, p, 64, 1, vreint_expected_f32_p64); TEST_VREINTERPRET(q, int, s, 8, 16, poly, p, 64, 2, vreint_expected_q_s8_p64); TEST_VREINTERPRET(q, int, s, 16, 8, poly, p, 64, 2, vreint_expected_q_s16_p64); @@ -195,7 +203,9 @@ int main (void) TEST_VREINTERPRET(q, uint, u, 64, 2, poly, p, 64, 2, vreint_expected_q_u64_p64); TEST_VREINTERPRET(q, poly, p, 8, 16, poly, p, 64, 2, vreint_expected_q_p8_p64); TEST_VREINTERPRET(q, poly, p, 16, 8, poly, p, 64, 2, vreint_expected_q_p16_p64); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) TEST_VREINTERPRET_FP(q, float, f, 16, 8, poly, p, 64, 2, vreint_expected_q_f16_p64); +#endif TEST_VREINTERPRET_FP(q, float, f, 32, 4, poly, p, 64, 2, vreint_expected_q_f32_p64); return 0; diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c index 282edd5..f5bf3bd 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c @@ -256,7 +256,9 @@ VECT_VAR_DECL_INIT(buffer_vld2_lane, uint, 32, 2); VECT_VAR_DECL_INIT(buffer_vld2_lane, uint, 64, 2); VECT_VAR_DECL_INIT(buffer_vld2_lane, poly, 8, 2); VECT_VAR_DECL_INIT(buffer_vld2_lane, poly, 16, 2); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) VECT_VAR_DECL_INIT(buffer_vld2_lane, float, 16, 2); +#endif VECT_VAR_DECL_INIT(buffer_vld2_lane, float, 32, 2); /* Input buffers for vld3_lane. */ @@ -270,7 +272,9 @@ VECT_VAR_DECL_INIT(buffer_vld3_lane, uint, 32, 3); VECT_VAR_DECL_INIT(buffer_vld3_lane, uint, 64, 3); VECT_VAR_DECL_INIT(buffer_vld3_lane, poly, 8, 3); VECT_VAR_DECL_INIT(buffer_vld3_lane, poly, 16, 3); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) VECT_VAR_DECL_INIT(buffer_vld3_lane, float, 16, 3); +#endif VECT_VAR_DECL_INIT(buffer_vld3_lane, float, 32, 3); /* Input buffers for vld4_lane. */ @@ -284,7 +288,9 @@ VECT_VAR_DECL_INIT(buffer_vld4_lane, uint, 32, 4); VECT_VAR_DECL_INIT(buffer_vld4_lane, uint, 64, 4); VECT_VAR_DECL_INIT(buffer_vld4_lane, poly, 8, 4); VECT_VAR_DECL_INIT(buffer_vld4_lane, poly, 16, 4); +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) VECT_VAR_DECL_INIT(buffer_vld4_lane, float, 16, 4); +#endif VECT_VAR_DECL_INIT(buffer_vld4_lane, float, 32, 4); void exec_vstX_lane (void) diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f16_indices_1.c index 46fa753..787664e 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f16_indices_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2_lane_f16_indices_1.c @@ -2,6 +2,7 @@ /* { dg-do compile } */ /* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-require-effective-target arm_neon_fp16_ok { target { arm*-*-* } } } */ float16x4x2_t f_vld2_lane_f16 (float16_t * p, float16x4x2_t v) diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f16_indices_1.c index f921d32..ce0569b 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f16_indices_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld2q_lane_f16_indices_1.c @@ -2,6 +2,7 @@ /* { dg-do compile } */ /* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-require-effective-target arm_neon_fp16_ok { target { arm*-*-* } } } */ float16x8x2_t f_vld2q_lane_f16 (float16_t * p, float16x8x2_t v) diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f16_indices_1.c index d068d79..5f2bd0a 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f16_indices_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3_lane_f16_indices_1.c @@ -2,6 +2,7 @@ /* { dg-do compile } */ /* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-require-effective-target arm_neon_fp16_ok { target { arm*-*-* } } } */ float16x4x3_t f_vld3_lane_f16 (float16_t * p, float16x4x3_t v) diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f16_indices_1.c index ed4d7d5..1fa19a1 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f16_indices_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld3q_lane_f16_indices_1.c @@ -2,6 +2,7 @@ /* { dg-do compile } */ /* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-require-effective-target arm_neon_fp16_ok { target { arm*-*-* } } } */ float16x8x3_t f_vld3q_lane_f16 (float16_t * p, float16x8x3_t v) diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f16_indices_1.c index b5d5adf..1f44645 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f16_indices_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4_lane_f16_indices_1.c @@ -2,6 +2,7 @@ /* { dg-do compile } */ /* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-require-effective-target arm_neon_fp16_ok { target { arm*-*-* } } } */ float16x4x4_t f_vld4_lane_f16 (float16_t * p, float16x4x4_t v) diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f16_indices_1.c index e9947d4..53d4a3e 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f16_indices_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vld4q_lane_f16_indices_1.c @@ -2,6 +2,7 @@ /* { dg-do compile } */ /* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-require-effective-target arm_neon_fp16_ok { target { arm*-*-* } } } */ float16x8x4_t f_vld4q_lane_f16 (float16_t * p, float16x8x4_t v) diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f16_indices_1.c index 93d6e5c..6c4ccf2 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f16_indices_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2_lane_f16_indices_1.c @@ -2,6 +2,7 @@ /* { dg-do compile } */ /* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-require-effective-target arm_neon_fp16_ok { target { arm*-*-* } } } */ void f_vst2_lane_f16 (float16_t * p, float16x4x2_t v) diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f16_indices_1.c index 729314e..a2f7abb 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f16_indices_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst2q_lane_f16_indices_1.c @@ -2,6 +2,7 @@ /* { dg-do compile } */ /* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-require-effective-target arm_neon_fp16_ok { target { arm*-*-* } } } */ void f_vst2q_lane_f16 (float16_t * p, float16x8x2_t v) diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f16_indices_1.c index 1f262a1..1538f65 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f16_indices_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3_lane_f16_indices_1.c @@ -2,6 +2,7 @@ /* { dg-do compile } */ /* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-require-effective-target arm_neon_fp16_ok { target { arm*-*-* } } } */ void f_vst3_lane_f16 (float16_t * p, float16x4x3_t v) diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f16_indices_1.c index 6c24a5e..8901c80 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f16_indices_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst3q_lane_f16_indices_1.c @@ -2,6 +2,7 @@ /* { dg-do compile } */ /* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-require-effective-target arm_neon_fp16_ok { target { arm*-*-* } } } */ void f_vst3q_lane_f16 (float16_t * p, float16x8x3_t v) diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f16_indices_1.c index 6ada55e..141e6b5 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f16_indices_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4_lane_f16_indices_1.c @@ -2,6 +2,7 @@ /* { dg-do compile } */ /* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-require-effective-target arm_neon_fp16_ok { target { arm*-*-* } } } */ void f_vst4_lane_f16 (float16_t * p, float16x4x4_t v) diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f16_indices_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f16_indices_1.c index 7327c03..2f18cd1 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f16_indices_1.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vst4q_lane_f16_indices_1.c @@ -2,6 +2,7 @@ /* { dg-do compile } */ /* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } } */ +/* { dg-require-effective-target arm_neon_fp16_ok { target { arm*-*-* } } } */ void f_vst4q_lane_f16 (float16_t * p, float16x8x4_t v)