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[209.132.180.131]) by mx.google.com with ESMTPS id ko10si4734610pbd.171.2015.01.20.07.25.28 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 20 Jan 2015 07:25:29 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-390010-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 9536 invoked by alias); 20 Jan 2015 15:25:09 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 9114 invoked by uid 89); 20 Jan 2015 15:24:58 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-qa0-f49.google.com Received: from mail-qa0-f49.google.com (HELO mail-qa0-f49.google.com) (209.85.216.49) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Tue, 20 Jan 2015 15:24:51 +0000 Received: by mail-qa0-f49.google.com with SMTP id v8so28593965qal.8 for ; Tue, 20 Jan 2015 07:24:49 -0800 (PST) MIME-Version: 1.0 X-Received: by 10.140.98.2 with SMTP id n2mr25605603qge.62.1421767488955; Tue, 20 Jan 2015 07:24:48 -0800 (PST) Received: by 10.140.84.176 with HTTP; Tue, 20 Jan 2015 07:24:48 -0800 (PST) In-Reply-To: References: <1421162314-25779-1-git-send-email-christophe.lyon@linaro.org> <1421162314-25779-10-git-send-email-christophe.lyon@linaro.org> <54B93739.1050300@arm.com> Date: Tue, 20 Jan 2015 16:24:48 +0100 Message-ID: Subject: Re: [[ARM/AArch64][testsuite] 09/36] Add vsubhn, vraddhn and vrsubhn tests. Split vaddhn.c into vXXXhn.inc and vaddhn.c to share code with other new tests. From: Christophe Lyon To: Tejas Belagod Cc: "gcc-patches@gcc.gnu.org" X-IsSubscribed: yes X-Original-Sender: christophe.lyon@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c03::229 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 On 16 January 2015 at 17:30, Christophe Lyon wrote: > On 16 January 2015 at 17:07, Tejas Belagod wrote: >> On 13/01/15 15:18, Christophe Lyon wrote: >>> >>> >>> * gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc: New file. >>> * gcc.target/aarch64/advsimd-intrinsics/vraddhn.c: New file. >>> * gcc.target/aarch64/advsimd-intrinsics/vrsubhn.c: New file. >>> * gcc.target/aarch64/advsimd-intrinsics/vsubhn.c: New file. >>> * gcc.target/aarch64/advsimd-intrinsics/vaddhn.c: Use code from >>> vXXXhn.inc. >>> >>> diff --git >>> a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc >>> b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc >>> new file mode 100644 >>> index 0000000..0dbcc92 >>> --- /dev/null >>> +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc >>> @@ -0,0 +1,50 @@ >>> +#define FNNAME1(NAME) exec_ ## NAME >>> +#define FNNAME(NAME) FNNAME1(NAME) >>> + >>> +void FNNAME (INSN_NAME) (void) >>> +{ >>> + /* Basic test: vec64=vaddhn(vec128_a, vec128_b), then store the result. >>> */ >>> +#define TEST_VADDHN1(INSN, T1, T2, W, W2, N) \ >>> + VECT_VAR(vector64, T1, W2, N) = INSN##_##T2##W(VECT_VAR(vector1, T1, W, >>> N), \ >>> + VECT_VAR(vector2, T1, W, >>> N)); \ >>> + vst1_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector64, T1, W2, >>> N)) >>> + >>> +#define TEST_VADDHN(INSN, T1, T2, W, W2, N) \ >>> + TEST_VADDHN1(INSN, T1, T2, W, W2, N) >>> + >> >> >> Minor nit. If this is a template file, maybe you should name this macro >> TEST_ADDHN as TEST_XXHN? Just that a template having an INSN name is >> confusing. > Agreed. > >>> +VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, >>> + 0x33, 0x33, 0x33, 0x33 }; >>> +VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 >>> }; >> >> >> Though never used, poly seems to have sneaked in here too. > Indeed, sorry for that. > I rushed to have as many tests as possible ready before stage 4, but > obviously I missed a few cleanups. > Here is an updated version, where I have removed a few more useless variables than you noticed: the [u]int64x1 as well as the 128 bits ones. Christophe. >> Otherwise, LGTM. >> >> Thanks, >> Tejas. >> >From 3acafe49a7402b859a88d1ef808b828a0acf96c4 Mon Sep 17 00:00:00 2001 From: Christophe Lyon Date: Tue, 2 Dec 2014 15:05:30 +0100 Subject: [[ARM/AArch64][testsuite] 09/36] Add vsubhn, vraddhn and vrsubhn tests. Split vaddhn.c into vXXXhn.inc and vaddhn.c to share code with other new tests. diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc new file mode 100644 index 0000000..5aabedd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn.inc @@ -0,0 +1,55 @@ +#define FNNAME1(NAME) exec_ ## NAME +#define FNNAME(NAME) FNNAME1(NAME) + +void FNNAME (INSN_NAME) (void) +{ + /* Basic test: vec64=vXXXhn(vec128_a, vec128_b), then store the result. */ +#define TEST_VXXXHN1(INSN, T1, T2, W, W2, N) \ + VECT_VAR(vector64, T1, W2, N) = INSN##_##T2##W(VECT_VAR(vector1, T1, W, N), \ + VECT_VAR(vector2, T1, W, N)); \ + vst1_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector64, T1, W2, N)) + +#define TEST_VXXXHN(INSN, T1, T2, W, W2, N) \ + TEST_VXXXHN1(INSN, T1, T2, W, W2, N) + + DECL_VARIABLE_64BITS_VARIANTS(vector64); + DECL_VARIABLE_128BITS_VARIANTS(vector1); + DECL_VARIABLE_128BITS_VARIANTS(vector2); + + clean_results (); + + /* Fill input vector1 and vector2 with arbitrary values */ + VDUP(vector1, q, int, s, 16, 8, 50*(UINT8_MAX+1)); + VDUP(vector1, q, int, s, 32, 4, 50*(UINT16_MAX+1)); + VDUP(vector1, q, int, s, 64, 2, 24*((uint64_t)UINT32_MAX+1)); + VDUP(vector1, q, uint, u, 16, 8, 3*(UINT8_MAX+1)); + VDUP(vector1, q, uint, u, 32, 4, 55*(UINT16_MAX+1)); + VDUP(vector1, q, uint, u, 64, 2, 3*((uint64_t)UINT32_MAX+1)); + + VDUP(vector2, q, int, s, 16, 8, (uint16_t)UINT8_MAX); + VDUP(vector2, q, int, s, 32, 4, (uint32_t)UINT16_MAX); + VDUP(vector2, q, int, s, 64, 2, (uint64_t)UINT32_MAX); + VDUP(vector2, q, uint, u, 16, 8, (uint16_t)UINT8_MAX); + VDUP(vector2, q, uint, u, 32, 4, (uint32_t)UINT16_MAX); + VDUP(vector2, q, uint, u, 64, 2, (uint64_t)UINT32_MAX); + + TEST_VXXXHN(INSN_NAME, int, s, 16, 8, 8); + TEST_VXXXHN(INSN_NAME, int, s, 32, 16, 4); + TEST_VXXXHN(INSN_NAME, int, s, 64, 32, 2); + TEST_VXXXHN(INSN_NAME, uint, u, 16, 8, 8); + TEST_VXXXHN(INSN_NAME, uint, u, 32, 16, 4); + TEST_VXXXHN(INSN_NAME, uint, u, 64, 32, 2); + + CHECK(TEST_MSG, int, 8, 8, PRIx8, expected, ""); + CHECK(TEST_MSG, int, 16, 4, PRIx16, expected, ""); + CHECK(TEST_MSG, int, 32, 2, PRIx32, expected, ""); + CHECK(TEST_MSG, uint, 8, 8, PRIx8, expected, ""); + CHECK(TEST_MSG, uint, 16, 4, PRIx16, expected, ""); + CHECK(TEST_MSG, uint, 32, 2, PRIx32, expected, ""); +} + +int main (void) +{ + FNNAME (INSN_NAME) (); + return 0; +} diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddhn.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddhn.c index 58fd5ea..96ae048 100644 --- a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddhn.c +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddhn.c @@ -8,100 +8,17 @@ #include #endif +#define INSN_NAME vaddhn +#define TEST_MSG "VADDHN" + /* Expected results. */ VECT_VAR_DECL(expected,int,8,8) [] = { 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32 }; VECT_VAR_DECL(expected,int,16,4) [] = { 0x32, 0x32, 0x32, 0x32 }; VECT_VAR_DECL(expected,int,32,2) [] = { 0x18, 0x18 }; -VECT_VAR_DECL(expected,int,64,1) [] = { 0x3333333333333333 }; VECT_VAR_DECL(expected,uint,8,8) [] = { 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3 }; VECT_VAR_DECL(expected,uint,16,4) [] = { 0x37, 0x37, 0x37, 0x37 }; VECT_VAR_DECL(expected,uint,32,2) [] = { 0x3, 0x3 }; -VECT_VAR_DECL(expected,uint,64,1) [] = { 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,8) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,4) [] = { 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,2) [] = { 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,int,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,int,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,int,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected,uint,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,uint,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,uint,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; -VECT_VAR_DECL(expected,uint,64,2) [] = { 0x3333333333333333, - 0x3333333333333333 }; -VECT_VAR_DECL(expected,poly,8,16) [] = { 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33, - 0x33, 0x33, 0x33, 0x33 }; -VECT_VAR_DECL(expected,poly,16,8) [] = { 0x3333, 0x3333, 0x3333, 0x3333, - 0x3333, 0x3333, 0x3333, 0x3333 }; -VECT_VAR_DECL(expected,hfloat,32,4) [] = { 0x33333333, 0x33333333, - 0x33333333, 0x33333333 }; - -#define INSN_NAME vaddhn -#define TEST_MSG "VADDHN" - -#define FNNAME1(NAME) exec_ ## NAME -#define FNNAME(NAME) FNNAME1(NAME) - -void FNNAME (INSN_NAME) (void) -{ - /* Basic test: vec64=vaddhn(vec128_a, vec128_b), then store the result. */ -#define TEST_VADDHN1(INSN, T1, T2, W, W2, N) \ - VECT_VAR(vector64, T1, W2, N) = INSN##_##T2##W(VECT_VAR(vector1, T1, W, N), \ - VECT_VAR(vector2, T1, W, N)); \ - vst1_##T2##W2(VECT_VAR(result, T1, W2, N), VECT_VAR(vector64, T1, W2, N)) - -#define TEST_VADDHN(INSN, T1, T2, W, W2, N) \ - TEST_VADDHN1(INSN, T1, T2, W, W2, N) - - DECL_VARIABLE_64BITS_VARIANTS(vector64); - DECL_VARIABLE_128BITS_VARIANTS(vector1); - DECL_VARIABLE_128BITS_VARIANTS(vector2); - - clean_results (); - - /* Fill input vector1 and vector2 with arbitrary values */ - VDUP(vector1, q, int, s, 16, 8, 50*(UINT8_MAX+1)); - VDUP(vector1, q, int, s, 32, 4, 50*(UINT16_MAX+1)); - VDUP(vector1, q, int, s, 64, 2, 24*((uint64_t)UINT32_MAX+1)); - VDUP(vector1, q, uint, u, 16, 8, 3*(UINT8_MAX+1)); - VDUP(vector1, q, uint, u, 32, 4, 55*(UINT16_MAX+1)); - VDUP(vector1, q, uint, u, 64, 2, 3*((uint64_t)UINT32_MAX+1)); - - VDUP(vector2, q, int, s, 16, 8, (uint16_t)UINT8_MAX); - VDUP(vector2, q, int, s, 32, 4, (uint32_t)UINT16_MAX); - VDUP(vector2, q, int, s, 64, 2, (uint64_t)UINT32_MAX); - VDUP(vector2, q, uint, u, 16, 8, (uint16_t)UINT8_MAX); - VDUP(vector2, q, uint, u, 32, 4, (uint32_t)UINT16_MAX); - VDUP(vector2, q, uint, u, 64, 2, (uint64_t)UINT32_MAX); - - TEST_VADDHN(INSN_NAME, int, s, 16, 8, 8); - TEST_VADDHN(INSN_NAME, int, s, 32, 16, 4); - TEST_VADDHN(INSN_NAME, int, s, 64, 32, 2); - TEST_VADDHN(INSN_NAME, uint, u, 16, 8, 8); - TEST_VADDHN(INSN_NAME, uint, u, 32, 16, 4); - TEST_VADDHN(INSN_NAME, uint, u, 64, 32, 2); - - CHECK_RESULTS (TEST_MSG, ""); -} -int main (void) -{ - FNNAME (INSN_NAME) (); - return 0; -} +#include "vXXXhn.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vraddhn.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vraddhn.c new file mode 100644 index 0000000..12bb3ba --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vraddhn.c @@ -0,0 +1,24 @@ +#include +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +#if defined(__cplusplus) +#include +#else +#include +#endif + +#define INSN_NAME vraddhn +#define TEST_MSG "VRADDHN" + +/* Expected results. */ +VECT_VAR_DECL(expected,int,8,8) [] = { 0x33, 0x33, 0x33, 0x33, + 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,int,16,4) [] = { 0x33, 0x33, 0x33, 0x33 }; +VECT_VAR_DECL(expected,int,32,2) [] = { 0x19, 0x19 }; +VECT_VAR_DECL(expected,uint,8,8) [] = { 0x4, 0x4, 0x4, 0x4, + 0x4, 0x4, 0x4, 0x4 }; +VECT_VAR_DECL(expected,uint,16,4) [] = { 0x38, 0x38, 0x38, 0x38 }; +VECT_VAR_DECL(expected,uint,32,2) [] = { 0x4, 0x4 }; + +#include "vXXXhn.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsubhn.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsubhn.c new file mode 100644 index 0000000..1ac1b17 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsubhn.c @@ -0,0 +1,24 @@ +#include +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +#if defined(__cplusplus) +#include +#else +#include +#endif + +#define INSN_NAME vrsubhn +#define TEST_MSG "VRSUBHN" + +/* Expected results. */ +VECT_VAR_DECL(expected,int,8,8) [] = { 0x31, 0x31, 0x31, 0x31, + 0x31, 0x31, 0x31, 0x31 }; +VECT_VAR_DECL(expected,int,16,4) [] = { 0x31, 0x31, 0x31, 0x31 }; +VECT_VAR_DECL(expected,int,32,2) [] = { 0x17, 0x17 }; +VECT_VAR_DECL(expected,uint,8,8) [] = { 0x2, 0x2, 0x2, 0x2, + 0x2, 0x2, 0x2, 0x2 }; +VECT_VAR_DECL(expected,uint,16,4) [] = { 0x36, 0x36, 0x36, 0x36 }; +VECT_VAR_DECL(expected,uint,32,2) [] = { 0x2, 0x2 }; + +#include "vXXXhn.inc" diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubhn.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubhn.c new file mode 100644 index 0000000..acecf41 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubhn.c @@ -0,0 +1,24 @@ +#include +#include "arm-neon-ref.h" +#include "compute-ref-data.h" + +#if defined(__cplusplus) +#include +#else +#include +#endif + +#define INSN_NAME vsubhn +#define TEST_MSG "VSUBHN" + +/* Expected results. */ +VECT_VAR_DECL(expected,int,8,8) [] = { 0x31, 0x31, 0x31, 0x31, + 0x31, 0x31, 0x31, 0x31 }; +VECT_VAR_DECL(expected,int,16,4) [] = { 0x31, 0x31, 0x31, 0x31 }; +VECT_VAR_DECL(expected,int,32,2) [] = { 0x17, 0x17 }; +VECT_VAR_DECL(expected,uint,8,8) [] = { 0x2, 0x2, 0x2, 0x2, + 0x2, 0x2, 0x2, 0x2 }; +VECT_VAR_DECL(expected,uint,16,4) [] = { 0x36, 0x36, 0x36, 0x36 }; +VECT_VAR_DECL(expected,uint,32,2) [] = { 0x2, 0x2 }; + +#include "vXXXhn.inc" -- 2.1.0