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[209.132.180.131]) by mx.google.com with ESMTPS id rb1si30372670pab.164.2015.01.14.03.27.33 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 14 Jan 2015 03:27:34 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-389201-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 25532 invoked by alias); 14 Jan 2015 11:27:20 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 25514 invoked by uid 89); 14 Jan 2015 11:27:18 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.2 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-qa0-f43.google.com Received: from mail-qa0-f43.google.com (HELO mail-qa0-f43.google.com) (209.85.216.43) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Wed, 14 Jan 2015 11:27:15 +0000 Received: by mail-qa0-f43.google.com with SMTP id v10so6155681qac.2 for ; Wed, 14 Jan 2015 03:27:13 -0800 (PST) MIME-Version: 1.0 X-Received: by 10.224.21.133 with SMTP id j5mr5489979qab.83.1421234833558; Wed, 14 Jan 2015 03:27:13 -0800 (PST) Received: by 10.140.91.202 with HTTP; Wed, 14 Jan 2015 03:27:13 -0800 (PST) Date: Wed, 14 Jan 2015 16:57:13 +0530 Message-ID: Subject: [RFC] Tighten memory type assumption in RTL combiner pass. From: Venkataramanan Kumar To: "gcc-patches@gcc.gnu.org" Cc: Maxim Kuvyrkov , segher@kernel.crashing.org, Richard Earnshaw , bernds@codesourcery.com X-IsSubscribed: yes X-Original-Sender: venkataramanan.kumar@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c03::22c as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 Hi all, When trying to debug GCC combiner pass with the test case in PR63949 ref https://gcc.gnu.org/bugzilla/show_bug.cgi?id=63949 I came across this code. This code in "make_compound_operation" assumes that all PLUS and MINUS RTX are "MEM" type for scalar int modes and tries to optimize based on that assumption. /* Select the code to be used in recursive calls. Once we are inside an address, we stay there. If we have a comparison, set to COMPARE, but once inside, go back to our default of SET. */ next_code = (code == MEM ? MEM : ((code == PLUS || code == MINUS) && SCALAR_INT_MODE_P (mode)) ? MEM : ((code == COMPARE || COMPARISON_P (x)) && XEXP (x, 1) == const0_rtx) ? COMPARE : in_code == COMPARE ? SET : in_code); next_code is passed as in_code via recursive calls to "make_compound_operation". Based on that we are converting shift pattern to MULT pattern. case ASHIFT: /* Convert shifts by constants into multiplications if inside an address. */ if (in_code == MEM && CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT && INTVAL (XEXP (x, 1)) >= 0 && SCALAR_INT_MODE_P (mode)) { Now I tried to tighten it further by adding check to see in_code is also MEM type. Not sure if this right thing to do. But this assumption about MEM seems to be very relaxed before. This passed bootstrap on x86_64 and GCC tests are not regressing. On Aarch64 passed bootstrap tests, test case in PR passed, but few tests failed (failed to generate adds and subs), because there are patterns (extended adds and subs) based on multiplication only in Aarch64 backend. if this change is correct then I may need to add patterns in Aarch64 based on shifts. Not sure about targets also. Requesting further comments/help about this. I am looking to get it fixed in stage 1. regards, Venkat. diff --git a/gcc/combine.c b/gcc/combine.c index 101cf35..1353f54 100644 --- a/gcc/combine.c +++ b/gcc/combine.c @@ -7696,7 +7696,8 @@ make_compound_operation (rtx x, enum rtx_code in_code) next_code = (code == MEM ? MEM : ((code == PLUS || code == MINUS) - && SCALAR_INT_MODE_P (mode)) ? MEM + && SCALAR_INT_MODE_P (mode) + && (in_code == MEM)) ? MEM : ((code == COMPARE || COMPARISON_P (x)) && XEXP (x, 1) == const0_rtx) ? COMPARE : in_code == COMPARE ? SET : in_code);