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[209.132.180.131]) by mx.google.com with ESMTPS id to5si9005655pac.7.2014.10.20.13.46.15 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 20 Oct 2014 13:46:15 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-381202-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 9560 invoked by alias); 20 Oct 2014 20:46:03 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 9550 invoked by uid 89); 20 Oct 2014 20:46:02 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.1 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW autolearn=ham version=3.3.2 X-HELO: mail-yh0-f51.google.com Received: from mail-yh0-f51.google.com (HELO mail-yh0-f51.google.com) (209.85.213.51) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Mon, 20 Oct 2014 20:46:01 +0000 Received: by mail-yh0-f51.google.com with SMTP id t59so3997275yho.38 for ; Mon, 20 Oct 2014 13:45:59 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.236.222.10 with SMTP id s10mr24132125yhp.102.1413837958963; Mon, 20 Oct 2014 13:45:58 -0700 (PDT) Received: by 10.170.111.204 with HTTP; Mon, 20 Oct 2014 13:45:58 -0700 (PDT) In-Reply-To: References: Date: Mon, 20 Oct 2014 13:45:58 -0700 Message-ID: Subject: Fwd: [PATCH/AARCH64] Add ThunderX -mcpu support From: Andrew Pinski To: gcc-patches@gcc.gnu.org X-Original-Sender: apinski@cavium.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c03::22c as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 Hi, This adds simple -mcpu=thunderx support. Right now we use the schedule model of cortex-a53 but we will submit a schedule model for ThunderX later on. Note ThunderX is an AARCH64 only processor so I created a new file to hold the cost tables for it rather than adding it to aarch-cost-tables.h. OK? Built and tested for aarch64-elf. Thanks, Andrew Pinski PS The corresponding binutils patch is located at https://sourceware.org/ml/binutils/2014-10/msg00170.html . ChangeLog: * doc/invoke.texi (AARCH64/mtune): Document thunderx as an available option also. * config/aarch64/aarch64-cost-tables.h: New file. * config/aarch64/aarch64-cores.def (thunderx): New core. * config/aarch64/aarch64-tune.md: Regenerate. * config/aarch64/aarch64.c: Include aarch64-cost-tables.h instead of config/arm/aarch-cost-tables.h. (thunderx_regmove_cost): New variable. (thunderx_tunings): New variable. Index: doc/invoke.texi =================================================================== --- doc/invoke.texi (revision 216416) +++ doc/invoke.texi (working copy) @@ -11808,7 +11808,7 @@ architecture. @opindex mtune Specify the name of the target processor for which GCC should tune the performance of the code. Permissible values for this option are: -@samp{generic}, @samp{cortex-a53}, @samp{cortex-a57}. +@samp{generic}, @samp{cortex-a53}, @samp{cortex-a57}, @samp{thunderx}. Additionally, this option can specify that GCC should tune the performance of the code for a big.LITTLE system. The only permissible value is Index: config/aarch64/aarch64-cost-tables.h =================================================================== --- config/aarch64/aarch64-cost-tables.h (revision 0) +++ config/aarch64/aarch64-cost-tables.h (revision 0) @@ -0,0 +1,131 @@ +/* RTX cost tables for aarch64. + + Copyright (C) 2014 Free Software Foundation, Inc. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 3, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING3. If not see + . */ + +#ifndef GCC_AARCH64_COST_TABLES_H +#define GCC_AARCH64_COST_TABLES_H + +#include "config/arm/aarch-cost-tables.h" + +/* ThunderX does not have implement AARCH32. */ +const struct cpu_cost_table thunderx_extra_costs = +{ + /* ALU */ + { + 0, /* Arith. */ + 0, /* Logical. */ + 0, /* Shift. */ + 0, /* Shift_reg. */ + COSTS_N_INSNS (1), /* Arith_shift. */ + COSTS_N_INSNS (1), /* Arith_shift_reg. */ + COSTS_N_INSNS (1), /* UNUSED: Log_shift. */ + COSTS_N_INSNS (1), /* UNUSED: Log_shift_reg. */ + 0, /* Extend. */ + COSTS_N_INSNS (1), /* Extend_arith. */ + 0, /* Bfi. */ + 0, /* Bfx. */ + COSTS_N_INSNS (5), /* Clz. */ + 0, /* rev. */ + 0, /* UNUSED: non_exec. */ + false /* UNUSED: non_exec_costs_exec. */ + }, + { + /* MULT SImode */ + { + COSTS_N_INSNS (3), /* Simple. */ + 0, /* Flag_setting. */ + 0, /* Extend. */ + 0, /* Add. */ + COSTS_N_INSNS (1), /* Extend_add. */ + COSTS_N_INSNS (21) /* Idiv. */ + }, + /* MULT DImode */ + { + COSTS_N_INSNS (3), /* Simple. */ + 0, /* Flag_setting. */ + 0, /* Extend. */ + 0, /* Add. */ + COSTS_N_INSNS (1), /* Extend_add. */ + COSTS_N_INSNS (37) /* Idiv. */ + }, + }, + /* LD/ST */ + { + COSTS_N_INSNS (2), /* Load. */ + COSTS_N_INSNS (2), /* Load_sign_extend. */ + COSTS_N_INSNS (2), /* Ldrd. */ + 0, /* N/A: Ldm_1st. */ + 0, /* N/A: Ldm_regs_per_insn_1st. */ + 0, /* N/A: Ldm_regs_per_insn_subsequent. */ + COSTS_N_INSNS (3), /* Loadf. */ + COSTS_N_INSNS (3), /* Loadd. */ + 0, /* N/A: Load_unaligned. */ + 0, /* Store. */ + 0, /* Strd. */ + 0, /* N/A: Stm_1st. */ + 0, /* N/A: Stm_regs_per_insn_1st. */ + 0, /* N/A: Stm_regs_per_insn_subsequent. */ + 0, /* Storef. */ + 0, /* Stored. */ + COSTS_N_INSNS (1) /* Store_unaligned. */ + }, + { + /* FP SFmode */ + { + COSTS_N_INSNS (11), /* Div. */ + COSTS_N_INSNS (5), /* Mult. */ + COSTS_N_INSNS (5), /* Mult_addsub. */ + COSTS_N_INSNS (5), /* Fma. */ + COSTS_N_INSNS (3), /* Addsub. */ + 0, /* Fpconst. */ + COSTS_N_INSNS (1), /* Neg. */ + 0, /* Compare. */ + COSTS_N_INSNS (5), /* Widen. */ + COSTS_N_INSNS (5), /* Narrow. */ + COSTS_N_INSNS (5), /* Toint. */ + COSTS_N_INSNS (5), /* Fromint. */ + COSTS_N_INSNS (1) /* Roundint. */ + }, + /* FP DFmode */ + { + COSTS_N_INSNS (21), /* Div. */ + COSTS_N_INSNS (5), /* Mult. */ + COSTS_N_INSNS (5), /* Mult_addsub. */ + COSTS_N_INSNS (5), /* Fma. */ + COSTS_N_INSNS (3), /* Addsub. */ + 0, /* Fpconst. */ + COSTS_N_INSNS (1), /* Neg. */ + 0, /* Compare. */ + COSTS_N_INSNS (5), /* Widen. */ + COSTS_N_INSNS (5), /* Narrow. */ + COSTS_N_INSNS (5), /* Toint. */ + COSTS_N_INSNS (5), /* Fromint. */ + COSTS_N_INSNS (1) /* Roundint. */ + } + }, + /* Vector */ + { + COSTS_N_INSNS (1) /* Alu. */ + } +}; + + + +#endif + Index: config/aarch64/aarch64-cores.def =================================================================== --- config/aarch64/aarch64-cores.def (revision 216416) +++ config/aarch64/aarch64-cores.def (working copy) @@ -36,6 +36,7 @@ AARCH64_CORE("cortex-a53", cortexa53, cortexa53, 8, AARCH64_FL_FPSIMD | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, cortexa53) AARCH64_CORE("cortex-a57", cortexa15, cortexa15, 8, AARCH64_FL_FPSIMD | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, cortexa57) +AARCH64_CORE("thunderx", thunderx, cortexa53, 8, AARCH64_FL_FPSIMD | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, thunderx) /* V8 big.LITTLE implementations. */ Index: config/aarch64/aarch64-tune.md =================================================================== --- config/aarch64/aarch64-tune.md (revision 216416) +++ config/aarch64/aarch64-tune.md (working copy) @@ -1,5 +1,5 @@ ;; -*- buffer-read-only: t -*- ;; Generated automatically by gentune.sh from aarch64-cores.def (define_attr "tune" - "cortexa53,cortexa15,cortexa57cortexa53" + "cortexa53,cortexa15,thunderx,cortexa57cortexa53" (const (symbol_ref "((enum attr_tune) aarch64_tune)"))) Index: config/aarch64/aarch64.c =================================================================== --- config/aarch64/aarch64.c (revision 216416) +++ config/aarch64/aarch64.c (working copy) @@ -65,7 +65,7 @@ #include "dwarf2.h" #include "cfgloop.h" #include "tree-vectorizer.h" -#include "config/arm/aarch-cost-tables.h" +#include "aarch64-cost-tables.h" #include "dumpfile.h" #include "builtins.h" @@ -242,6 +242,14 @@ static const struct cpu_regmove_cost cor NAMED_PARAM (FP2FP, 2) }; +static const struct cpu_regmove_cost thunderx_regmove_cost = +{ + NAMED_PARAM (GP2GP, 2), + NAMED_PARAM (GP2FP, 2), + NAMED_PARAM (FP2GP, 6), + NAMED_PARAM (FP2FP, 4) +}; + /* Generic costs for vector insn classes. */ #if HAVE_DESIGNATED_INITIALIZERS && GCC_VERSION >= 2007 __extension__ @@ -315,6 +323,16 @@ static const struct tune_params cortexa5 NAMED_PARAM (issue_rate, 3) }; +static const struct tune_params thunderx_tunings = +{ + &thunderx_extra_costs, + &generic_addrcost_table, + &thunderx_regmove_cost, + &generic_vector_cost, + NAMED_PARAM (memmov_cost, 6), + NAMED_PARAM (issue_rate, 2) +}; + /* A processor implementing AArch64. */ struct processor {