From patchwork Fri May 1 13:56:47 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yvan Roux X-Patchwork-Id: 47886 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-la0-f72.google.com (mail-la0-f72.google.com [209.85.215.72]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 656D92121F for ; Fri, 1 May 2015 13:57:14 +0000 (UTC) Received: by labgx2 with SMTP id gx2sf27528983lab.1 for ; Fri, 01 May 2015 06:57:13 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:mailing-list:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:sender :delivered-to:mime-version:in-reply-to:references:date:message-id :subject:from:to:cc:content-type:x-original-sender :x-original-authentication-results; bh=YHRnaVX4P3zul1ByxUVzW/uzbzvt0T0kCQUWPrM7bmY=; b=OQCJedtX/XeMM5FUXnWa0VLvL6EAjFFMEk+HNvnH8ecg+/I5Oyualb8nUkz1KH9YAd hVlupNaFr6IVlRC0/3xIhZgcAKyqNGxazxxEqVf+ectA6162ecCO6dU+9Zrx1owpfLet 1XVJr+8ieAmv1cFGkWCv8t6M3SKEd2Fyc2H8U0rWhxj68jl0hBHWEK71DQJgye+dcWxE KvtqbUxFarW7I+qqZth86sOZCO7NnMfCb6wdd4516Mp5vJoVph6aSNsDm33pG6vE9roS TPUkOnu3zsWASXVV3W7UBZZgdiltu2szHHVCRv6JIOw/KX8gTqMaUIKX2dwYLAlENPxk 1tjw== X-Gm-Message-State: ALoCoQnkmFYwvfAZEkkhZkKjzS4HlYrO8xNLbDGP2x8rCKFCRXvx95lScYZ70VVkOpRkEtKZUErR X-Received: by 10.112.203.168 with SMTP id kr8mr7740955lbc.10.1430488633177; Fri, 01 May 2015 06:57:13 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.42.137 with SMTP id o9ls463460lal.16.gmail; Fri, 01 May 2015 06:57:12 -0700 (PDT) X-Received: by 10.152.42.242 with SMTP id r18mr8370955lal.8.1430488632894; Fri, 01 May 2015 06:57:12 -0700 (PDT) Received: from mail-lb0-x233.google.com (mail-lb0-x233.google.com. [2a00:1450:4010:c04::233]) by mx.google.com with ESMTPS id az14si3993305lab.154.2015.05.01.06.57.12 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 01 May 2015 06:57:12 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c04::233 as permitted sender) client-ip=2a00:1450:4010:c04::233; Received: by lbbuc2 with SMTP id uc2so65156080lbb.2 for ; Fri, 01 May 2015 06:57:12 -0700 (PDT) X-Received: by 10.152.4.72 with SMTP id i8mr8588692lai.32.1430488632667; Fri, 01 May 2015 06:57:12 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.67.65 with SMTP id l1csp298715lbt; Fri, 1 May 2015 06:57:11 -0700 (PDT) X-Received: by 10.66.156.225 with SMTP id wh1mr18436648pab.100.1430488630224; Fri, 01 May 2015 06:57:10 -0700 (PDT) Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id hj2si8067080pbc.103.2015.05.01.06.57.09 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 01 May 2015 06:57:10 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-396612-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 13015 invoked by alias); 1 May 2015 13:56:54 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 13004 invoked by uid 89); 1 May 2015 13:56:53 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.3 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-wi0-f176.google.com Received: from mail-wi0-f176.google.com (HELO mail-wi0-f176.google.com) (209.85.212.176) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Fri, 01 May 2015 13:56:51 +0000 Received: by wizk4 with SMTP id k4so53352977wiz.1 for ; Fri, 01 May 2015 06:56:48 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.194.236.66 with SMTP id us2mr18622460wjc.54.1430488607855; Fri, 01 May 2015 06:56:47 -0700 (PDT) Received: by 10.28.4.204 with HTTP; Fri, 1 May 2015 06:56:47 -0700 (PDT) In-Reply-To: References: Date: Fri, 1 May 2015 15:56:47 +0200 Message-ID: Subject: Re: [PATCH, AArch64] Add Cortex-A53 erratum 843419 configure-time option From: Yvan Roux To: Marcus Shawcroft Cc: "gcc-patches@gcc.gnu.org" , Maxim Kuvyrkov , Richard Earnshaw , James Greenhalgh X-IsSubscribed: yes X-Original-Sender: yvan.roux@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c04::233 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 On 1 May 2015 at 13:39, Yvan Roux wrote: > Hi Marcus, > > (Sorry wanted to cc you in my first mail but seems that gmail prefers > Maxim to Marcus ! ;) > > On 1 May 2015 at 13:11, Marcus Shawcroft wrote: >> On 1 May 2015 at 10:11, Yvan Roux wrote: >>> Hi all, >>> >>> As described in the thread bellow, there is a link-time workaround for >>> an erratum (843419) of some early revision of Cortex-A53. Similarly >>> to what was done for a previous erratum, this patch adds a new >>> configure-time option --enable-fix-cortex-a53-843419 that pass down >>> the linker option --fix-cortex-a53-843419. >>> >>> I haven't implemented flags to explicitly disable/enable it during >>> compilation as it is only a linker workaround, but I can do it if you >>> think it's necessary. >> >> Hi Yvan, >> >> In the case of the 835769 erratum, providing such GCC configury made >> (some) sense because the workaround included both a GCC and an LD >> component. GCC in effect needed the option to control GCC behaviour >> aswell as LD behaviour. The same is not true of 843419. The net effect >> of the proposed patch here is to provide a configure option in GCC to >> change the default behaviour of LD, with no other purpose within GCC >> itself. This seems rather bizarre to me. I would have thought that if >> the sole objective is to change the default behaviour of LD, then >> there should be configure time options on LD, rather than GCC. > > Yes indeed. > >> That said, I can also see that providing consistent behaviour across >> these various work around configure options and consistent run time >> options for the user will reduce confusion in the future, both for >> folks building toolchains and for the folks using them. From this >> perspective I think it would be better to go with this patch *and* >> include the flags explicitly such the both of the current workaround >> have equivalent configury behaviour and have equivalent user flags at >> run time. > > Ok I'll add the -mfix-cortex-a53-843419 flags to be consistent. Here is the new patch, I kept the "Report" property for the flag even if nothing is changed in the assembly generated, but I think it's good to have the info. Cheers, Yvan 2015-05-01 Yvan Roux * configure.ac: Add --enable-fix-cortex-a53-843419 option. * configure: Regenerate. * config/aarch64/aarch64-elf-raw.h (CA53_ERR_843419_SPEC): Define. (LINK_SPEC): Include CA53_ERR_843419_SPEC. * config/aarch64/aarch64-linux.h (CA53_ERR_843419_SPEC): Define. (LINK_SPEC): Include CA53_ERR_843419_SPEC. * doc/install.texi (aarch64*-*-*): Document new --enable-fix-cortex-a53-843419 option * config/aarch64/aarch64.opt (mfix-cortex-a53-843419): New option. * doc/invoke.texi (AArch64 Options): Document -mfix-cortex-a53-843419 and -mno-fix-cortex-a53-8434199 options. > > Cheers > Yvan > >> Cheers >> /Marcus >> >>> >>> https://sourceware.org/ml/binutils-cvs/2015-04/msg00012.html >>> >>> Is it ok for trunk and/or branches ? >>> >>> Thanks, >>> Yvan >>> >>> 2015-05-01 Yvan Roux >>> >>> * configure.ac: Add --enable-fix-cortex-a53-843419 option. >>> * configure: Regenerate. >>> * config/aarch64/aarch64-elf-raw.h (CA53_ERR_843419_SPEC): Define. >>> (LINK_SPEC): Include CA53_ERR_843419_SPEC. >>> * config/aarch64/aarch64-linux.h (CA53_ERR_843419_SPEC): Define. >>> (LINK_SPEC): Include CA53_ERR_843419_SPEC. >>> * doc/install.texi (aarch64*-*-*): Document >>> new --enable-fix-cortex-a53-843419 option. diff --git a/gcc/config/aarch64/aarch64-elf-raw.h b/gcc/config/aarch64/aarch64-elf-raw.h index ebeeb50..bd5e51c 100644 --- a/gcc/config/aarch64/aarch64-elf-raw.h +++ b/gcc/config/aarch64/aarch64-elf-raw.h @@ -35,10 +35,19 @@ " %{mfix-cortex-a53-835769:--fix-cortex-a53-835769}" #endif +#ifdef TARGET_FIX_ERR_A53_843419_DEFAULT +#define CA53_ERR_843419_SPEC \ + " %{!mno-fix-cortex-a53-843419:--fix-cortex-a53-843419}" +#else +#define CA53_ERR_843419_SPEC \ + " %{mfix-cortex-a53-843419:--fix-cortex-a53-843419}" +#endif + #ifndef LINK_SPEC #define LINK_SPEC "%{mbig-endian:-EB} %{mlittle-endian:-EL} -X \ -maarch64elf%{mabi=ilp32*:32}%{mbig-endian:b}" \ - CA53_ERR_835769_SPEC + CA53_ERR_835769_SPEC \ + CA53_ERR_843419_SPEC #endif #endif /* GCC_AARCH64_ELF_RAW_H */ diff --git a/gcc/config/aarch64/aarch64-linux.h b/gcc/config/aarch64/aarch64-linux.h index 9abb252..7973268 100644 --- a/gcc/config/aarch64/aarch64-linux.h +++ b/gcc/config/aarch64/aarch64-linux.h @@ -49,8 +49,17 @@ " %{mfix-cortex-a53-835769:--fix-cortex-a53-835769}" #endif +#ifdef TARGET_FIX_ERR_A53_843419_DEFAULT +#define CA53_ERR_843419_SPEC \ + " %{!mno-fix-cortex-a53-843419:--fix-cortex-a53-843419}" +#else +#define CA53_ERR_843419_SPEC \ + " %{mfix-cortex-a53-843419:--fix-cortex-a53-843419}" +#endif + #define LINK_SPEC LINUX_TARGET_LINK_SPEC \ - CA53_ERR_835769_SPEC + CA53_ERR_835769_SPEC \ + CA53_ERR_843419_SPEC #define GNU_USER_TARGET_MATHFILE_SPEC \ "%{Ofast|ffast-math|funsafe-math-optimizations:crtfastmath.o%s}" diff --git a/gcc/config/aarch64/aarch64.opt b/gcc/config/aarch64/aarch64.opt index f2ef124..6d72ac2 100644 --- a/gcc/config/aarch64/aarch64.opt +++ b/gcc/config/aarch64/aarch64.opt @@ -71,6 +71,10 @@ mfix-cortex-a53-835769 Target Report Var(aarch64_fix_a53_err835769) Init(2) Workaround for ARM Cortex-A53 Erratum number 835769 +mfix-cortex-a53-843419 +Target Report +Workaround for ARM Cortex-A53 Erratum number 843419 + mlittle-endian Target Report RejectNegative InverseMask(BIG_END) Assume target CPU is configured as little endian diff --git a/gcc/configure b/gcc/configure index 84f58ce..e563e94 100755 --- a/gcc/configure +++ b/gcc/configure @@ -923,6 +923,7 @@ enable_gnu_indirect_function enable_initfini_array enable_comdat enable_fix_cortex_a53_835769 +enable_fix_cortex_a53_843419 with_glibc_version enable_gnu_unique_object enable_linker_build_id @@ -1648,6 +1649,14 @@ Optional Features: disable workaround for AArch64 Cortex-A53 erratum 835769 by default + + --enable-fix-cortex-a53-843419 + enable workaround for AArch64 Cortex-A53 erratum + 843419 by default + --disable-fix-cortex-a53-843419 + disable workaround for AArch64 Cortex-A53 erratum + 843419 by default + --enable-gnu-unique-object enable the use of the @gnu_unique_object ELF extension on glibc systems @@ -18153,7 +18162,7 @@ else lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <<_LT_EOF -#line 18156 "configure" +#line 18165 "configure" #include "confdefs.h" #if HAVE_DLFCN_H @@ -18259,7 +18268,7 @@ else lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <<_LT_EOF -#line 18262 "configure" +#line 18271 "configure" #include "confdefs.h" #if HAVE_DLFCN_H @@ -24102,6 +24111,25 @@ if test "${enable_fix_cortex_a53_835769+set}" = set; then : fi + # Enable default workaround for AArch64 Cortex-A53 erratum 843419. + # Check whether --enable-fix-cortex-a53-843419 was given. +if test "${enable_fix_cortex_a53_843419+set}" = set; then : + enableval=$enable_fix_cortex_a53_843419; + case $enableval in + yes) + tm_defines="${tm_defines} TARGET_FIX_ERR_A53_843419_DEFAULT=1" + ;; + no) + ;; + *) + as_fn_error "'$enableval' is an invalid value for --enable-fix-cortex-a53-843419.\ + Valid choices are 'yes' and 'no'." "$LINENO" 5 + ;; + + esac + +fi + ;; # All TARGET_ABI_OSF targets. diff --git a/gcc/configure.ac b/gcc/configure.ac index 7fb6131..55fe633 100644 --- a/gcc/configure.ac +++ b/gcc/configure.ac @@ -3592,6 +3592,29 @@ AS_HELP_STRING([--disable-fix-cortex-a53-835769], esac ], []) + # Enable default workaround for AArch64 Cortex-A53 erratum 843419. + AC_ARG_ENABLE(fix-cortex-a53-843419, + [ +AS_HELP_STRING([--enable-fix-cortex-a53-843419], + [enable workaround for AArch64 Cortex-A53 erratum 843419 by default]) +AS_HELP_STRING([--disable-fix-cortex-a53-843419], + [disable workaround for AArch64 Cortex-A53 erratum 843419 by default]) + ], + [ + case $enableval in + yes) + tm_defines="${tm_defines} TARGET_FIX_ERR_A53_843419_DEFAULT=1" + ;; + no) + ;; + *) + AC_MSG_ERROR(['$enableval' is an invalid value for --enable-fix-cortex-a53-843419.\ + Valid choices are 'yes' and 'no'.]) + ;; + + esac + ], + []) ;; # All TARGET_ABI_OSF targets. diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi index 783116e..169ecf1 100644 --- a/gcc/doc/install.texi +++ b/gcc/doc/install.texi @@ -3408,13 +3408,24 @@ not support option @option{-mabi=ilp32}. To enable a workaround for the Cortex-A53 erratum number 835769 by default (for all CPUs regardless of -mcpu option given) at configure time use the @option{--enable-fix-cortex-a53-835769} option. This will enable the fix by -default and can be explicitly disabled during during compilation by passing the +default and can be explicitly disabled during compilation by passing the @option{-mno-fix-cortex-a53-835769} option. Conversely, @option{--disable-fix-cortex-a53-835769} will disable the workaround by default. The workaround is disabled by default if neither of @option{--enable-fix-cortex-a53-835769} or @option{--disable-fix-cortex-a53-835769} is given at configure time. +To enable a workaround for the Cortex-A53 erratum number 843419 by default +(for all CPUs regardless of -mcpu option given) at configure time use the +@option{--enable-fix-cortex-a53-843419} option. This erratum workaround is +made at link time and enabling it by default in GCC will only pass the +corresponding flag to the linker. It can be explicitly disabled during +compilation by passing the @option{-mno-fix-cortex-a53-835769} option. +Conversely, @option{--disable-fix-cortex-a53-843419} will disable the +workaround by default. The workaround is disabled by default if neither of +@option{--enable-fix-cortex-a53-843419} or +@option{--disable-fix-cortex-a53-843419} is given at configure time. + @html
@end html diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 7d2f6e5..712c187 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -512,6 +512,7 @@ Objective-C and Objective-C++ Dialects}. -momit-leaf-frame-pointer -mno-omit-leaf-frame-pointer @gol -mtls-dialect=desc -mtls-dialect=traditional @gol -mfix-cortex-a53-835769 -mno-fix-cortex-a53-835769 @gol +-mfix-cortex-a53-843419 -mno-fix-cortex-a53-843419 @gol -march=@var{name} -mcpu=@var{name} -mtune=@var{name}} @emph{Adapteva Epiphany Options} @@ -12324,6 +12325,14 @@ Enable or disable the workaround for the ARM Cortex-A53 erratum number 835769. This involves inserting a NOP instruction between memory instructions and 64-bit integer multiply-accumulate instructions. +@item -mfix-cortex-a53-843419 +@itemx -mno-fix-cortex-a53-843419 +@opindex mfix-cortex-a53-843419 +@opindex mno-fix-cortex-a53-843419 +Enable or disable the workaround for the ARM Cortex-A53 erratum number 843419. +This erratum workaround is made at link time and this will only pass the +corresponding flag to the linker. + @item -march=@var{name} @opindex march Specify the name of the target architecture, optionally suffixed by one or