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[209.132.180.131]) by mx.google.com with ESMTPS id fs8si354543pdb.76.2015.03.24.12.54.27 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 24 Mar 2015 12:54:28 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-394025-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 43935 invoked by alias); 24 Mar 2015 19:53:44 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 43795 invoked by uid 89); 24 Mar 2015 19:53:44 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.1 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-ob0-f176.google.com Received: from mail-ob0-f176.google.com (HELO mail-ob0-f176.google.com) (209.85.214.176) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Tue, 24 Mar 2015 19:53:42 +0000 Received: by obdfc2 with SMTP id fc2so2851046obd.3 for ; Tue, 24 Mar 2015 12:53:40 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.182.255.195 with SMTP id as3mr4650914obd.56.1427226819404; Tue, 24 Mar 2015 12:53:39 -0700 (PDT) Received: by 10.202.54.66 with HTTP; Tue, 24 Mar 2015 12:53:39 -0700 (PDT) Date: Tue, 24 Mar 2015 20:53:39 +0100 Message-ID: Subject: [PATCH, ARM] Fix arm_subsi3_insn alternatives From: Yvan Roux To: "gcc-patches@gcc.gnu.org" , Ramana Radhakrishnan , Richard Earnshaw X-IsSubscribed: yes X-Original-Sender: yvan.roux@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c03::230 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 Hi, after the issue with duplicated alternatives exhibited by PR64208, I checked the arm.md file and found that *arm_subsi3_insn has a duplication where alt 4 is (r,rI,r) and alt 6 is (r,r,r), this results in emitting an rsb instruction instead of a sub one, but it has also an impact on scheduling as the type attribute affected to alt 4 is alu_imm when it could only involve registers. This is fixed by this small patch. Cross builded and regtested for arm/armeb targets. Ok for trunk (maybe for stage 1 as no PR is attached to that) ? Cheers, Yvan 2105-03-24 Yvan Roux * config/arm/arm.md ("*arm_subsi3_insn"): Fixed redundant alternatives. diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 164ac13..b4e50c2 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -1177,9 +1177,9 @@ ; ??? Check Thumb-2 split length (define_insn_and_split "*arm_subsi3_insn" - [(set (match_operand:SI 0 "s_register_operand" "=l,l ,l ,l ,r ,r,r,rk,r") - (minus:SI (match_operand:SI 1 "reg_or_int_operand" "l ,0 ,l ,Pz,rI,r,r,k ,?n") - (match_operand:SI 2 "reg_or_int_operand" "l ,Py,Pd,l ,r ,I,r,r ,r")))] + [(set (match_operand:SI 0 "s_register_operand" "=l,l ,l ,l ,r,r,r,rk,r") + (minus:SI (match_operand:SI 1 "reg_or_int_operand" "l ,0 ,l ,Pz,I,r,r,k ,?n") + (match_operand:SI 2 "reg_or_int_operand" "l ,Py,Pd,l ,r,I,r,r ,r")))] "TARGET_32BIT" "@ sub%?\\t%0, %1, %2