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[209.132.180.131]) by mx.google.com with ESMTPS id ed1si20488907pbb.2.2014.06.23.00.01.15 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 23 Jun 2014 00:01:16 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-370792-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 16648 invoked by alias); 23 Jun 2014 07:01:03 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 16632 invoked by uid 89); 23 Jun 2014 07:01:03 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-lb0-f174.google.com Received: from mail-lb0-f174.google.com (HELO mail-lb0-f174.google.com) (209.85.217.174) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Mon, 23 Jun 2014 07:00:29 +0000 Received: by mail-lb0-f174.google.com with SMTP id u10so3918139lbd.33 for ; Mon, 23 Jun 2014 00:00:26 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.152.5.4 with SMTP id o4mr510212lao.64.1403506825904; Mon, 23 Jun 2014 00:00:25 -0700 (PDT) Received: by 10.112.13.36 with HTTP; Mon, 23 Jun 2014 00:00:25 -0700 (PDT) Date: Mon, 23 Jun 2014 15:00:25 +0800 Message-ID: Subject: [PATCH, 7/10] aarch64: add function to output ccmp insn From: Zhenqiang Chen To: "gcc-patches@gcc.gnu.org" X-IsSubscribed: yes X-Original-Sender: zhenqiang.chen@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2607:f8b0:400c:c01::231 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 Hi, The patch adds three help functions to output ccmp instructions. OK for trunk? Thanks! -Zhenqiang ChangeLog: 2014-06-23 Zhenqiang Chen * config/aarch64/aarch64-protos.h (aarch64_output_ccmp): New prototype. * config/aarch64/aarch64.c (aarch64_code_to_nzcv): New function. (aarch64_mode_to_condition_code): New function. (aarch64_output_ccmp): New function. diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index 997ff50..ff1a0f4 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -247,6 +247,7 @@ void aarch64_print_operand (FILE *, rtx, char); void aarch64_print_operand_address (FILE *, rtx); bool aarch64_uimm5 (HOST_WIDE_INT); +const char* aarch64_output_ccmp (rtx *, bool, int); /* Initialize builtins for SIMD intrinsics. */ void init_aarch64_simd_builtins (void); diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index e5ede6e..5fe4826 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -9602,6 +9602,137 @@ aarch64_uimm5 (HOST_WIDE_INT val) return (val & (HOST_WIDE_INT) 0x1f) == val; } +/* N Z C V. */ +#define AARCH64_CC_V 1 +#define AARCH64_CC_C (1 << 1) +#define AARCH64_CC_Z (1 << 2) +#define AARCH64_CC_N (1 << 3) + +static unsigned int +aarch64_code_to_nzcv (enum rtx_code code, bool inverse) +{ + switch (code) + { + case NE: /* NE, Z == 0. */ + return inverse ? AARCH64_CC_Z : 0; + case EQ: /* EQ, Z == 1. */ + return inverse ? 0 : AARCH64_CC_Z; + case LE: /* LE, !(Z == 0 && N == V). */ + return inverse ? AARCH64_CC_N | AARCH64_CC_V : AARCH64_CC_Z; + case GT: /* GT, Z == 0 && N == V. */ + return inverse ? AARCH64_CC_Z : AARCH64_CC_N | AARCH64_CC_V; + case LT: /* LT, N != V. */ + return inverse ? AARCH64_CC_N | AARCH64_CC_V : AARCH64_CC_N; + case GE: /* GE, N == V. */ + return inverse ? AARCH64_CC_N : AARCH64_CC_N | AARCH64_CC_V; + case LEU: /* LS, !(C == 1 && Z == 0). */ + return inverse ? AARCH64_CC_C: AARCH64_CC_Z; + case GTU: /* HI, C ==1 && Z == 0. */ + return inverse ? AARCH64_CC_Z : AARCH64_CC_C; + case LTU: /* CC, C == 0. */ + return inverse ? AARCH64_CC_C : 0; + case GEU: /* CS, C == 1. */ + return inverse ? 0 : AARCH64_CC_C; + default: + gcc_unreachable (); + return 0; + } +} + +static unsigned +aarch64_mode_to_condition_code (enum machine_mode mode, bool inverse) +{ + switch (mode) + { + case CC_DNEmode: + return inverse ? aarch64_get_condition_code_1 (CCmode, EQ) + : aarch64_get_condition_code_1 (CCmode, NE); + case CC_DEQmode: + return inverse ? aarch64_get_condition_code_1 (CCmode, NE) + : aarch64_get_condition_code_1 (CCmode, EQ); + case CC_DLEmode: + return inverse ? aarch64_get_condition_code_1 (CCmode, GT) + : aarch64_get_condition_code_1 (CCmode, LE); + case CC_DGTmode: + return inverse ? aarch64_get_condition_code_1 (CCmode, LE) + : aarch64_get_condition_code_1 (CCmode, GT); + case CC_DLTmode: + return inverse ? aarch64_get_condition_code_1 (CCmode, GE) + : aarch64_get_condition_code_1 (CCmode, LT); + case CC_DGEmode: + return inverse ? aarch64_get_condition_code_1 (CCmode, LT) + : aarch64_get_condition_code_1 (CCmode, GE); + case CC_DLEUmode: + return inverse ? aarch64_get_condition_code_1 (CCmode, GTU) + : aarch64_get_condition_code_1 (CCmode, LEU); + case CC_DGTUmode: + return inverse ? aarch64_get_condition_code_1 (CCmode, LEU) + : aarch64_get_condition_code_1 (CCmode, GTU); + case CC_DLTUmode: + return inverse ? aarch64_get_condition_code_1 (CCmode, GEU) + : aarch64_get_condition_code_1 (CCmode, LTU); + case CC_DGEUmode: + return inverse ? aarch64_get_condition_code_1 (CCmode, LTU) + : aarch64_get_condition_code_1 (CCmode, GEU); + default: + gcc_unreachable (); + } +} + +const char * +aarch64_output_ccmp (rtx *operands, bool is_and, int which_alternative) +{ + char buf[32]; + rtx cc = operands[0]; + enum rtx_code code = GET_CODE (operands[5]); + unsigned char nzcv = aarch64_code_to_nzcv (code, is_and); + enum machine_mode mode = GET_MODE (cc); + unsigned int cond_code = aarch64_mode_to_condition_code (mode, !is_and); + + gcc_assert (GET_MODE (operands[2]) == SImode + || GET_MODE (operands[2]) == DImode); + + if (GET_MODE (operands[2]) == SImode) + switch (which_alternative) + { + case 0: + snprintf (buf, sizeof (buf), "ccmp\t%%w2, %%w3, #%u, %s", + nzcv, aarch64_condition_codes[cond_code]); + break; + case 1: + snprintf (buf, sizeof (buf), "ccmp\t%%w2, #%%3, #%u, %s", + nzcv, aarch64_condition_codes[cond_code]); + break; + case 2: + snprintf (buf, sizeof (buf), "ccmn\t%%w2, #%%n3, #%u, %s", + nzcv, aarch64_condition_codes[cond_code]); + break; + default: + gcc_unreachable (); + } + else + switch (which_alternative) + { + case 0: + snprintf (buf, sizeof (buf), "ccmp\t%%x2, %%x3, #%u, %s", + nzcv, aarch64_condition_codes[cond_code]); + break; + case 1: + snprintf (buf, sizeof (buf), "ccmp\t%%x2, #%%3, #%u, %s", + nzcv, aarch64_condition_codes[cond_code]); + break; + case 2: + snprintf (buf, sizeof (buf), "ccmn\t%%x2, #%%n3, #%u, %s", + nzcv, aarch64_condition_codes[cond_code]); + break; + default: + gcc_unreachable (); + } + + output_asm_insn (buf, operands); + return ""; +} + #undef TARGET_ADDRESS_COST #define TARGET_ADDRESS_COST aarch64_address_cost