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[209.132.180.131]) by mx.google.com with ESMTPS id my2si994480pbc.197.2014.03.27.01.44.33 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 27 Mar 2014 01:44:34 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-364061-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 3918 invoked by alias); 27 Mar 2014 08:44:19 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 3877 invoked by uid 89); 27 Mar 2014 08:44:18 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-la0-f46.google.com Received: from mail-la0-f46.google.com (HELO mail-la0-f46.google.com) (209.85.215.46) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Thu, 27 Mar 2014 08:44:12 +0000 Received: by mail-la0-f46.google.com with SMTP id hr17so2364061lab.33 for ; Thu, 27 Mar 2014 01:44:09 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.152.210.70 with SMTP id ms6mr289093lac.5.1395909848914; Thu, 27 Mar 2014 01:44:08 -0700 (PDT) Received: by 10.112.135.105 with HTTP; Thu, 27 Mar 2014 01:44:08 -0700 (PDT) In-Reply-To: <20140326074535.GE1817@tucnak.redhat.com> References: <20140326070044.GD1817@tucnak.redhat.com> <20140326074535.GE1817@tucnak.redhat.com> Date: Thu, 27 Mar 2014 16:44:08 +0800 Message-ID: Subject: Re: [PATCH] Fix PR rtl-optimization/pr60663 From: Zhenqiang Chen To: Jakub Jelinek Cc: "gcc-patches@gcc.gnu.org" X-IsSubscribed: yes X-Original-Sender: zhenqiang.chen@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 2607:f8b0:400c:c03::230 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 On 26 March 2014 15:45, Jakub Jelinek wrote: > On Wed, Mar 26, 2014 at 03:30:44PM +0800, Zhenqiang Chen wrote: >> Agree. CSE should never modify asm insns to drop some of the outputs. > > So the right fix is top prevent this from happening, not papering over about > it. >> >> But in this case, CSE does not drop any of the outputs. It just takes >> the SRC of a set and replace the reference of the set. And the >> instruction validation tells CSE that it is legal instruction after >> replacement. (The original correct asm insn is optimized away after >> this replacement) >> >> I think it is common for most rtl-optimizations to do such kind of >> validation. So to avoid such kind of bug, check_asm_operands must tell >> the optimizer the asm is illegal. > > As it is wrong if CSE does that even with asm ("" : "=r" (i), "=r" (j));, > your patch is not the right place to fix this. CSE just must check where > the ASM_OPERANDS is coming from and if it comes from a PARALLEL with > multiple outputs, either give up or duplicate all outputs (if it makes sense > at all). Or just don't enter into the hash tables ASM_OPERANDS with > multiple outputs. Patch is updated: Thanks! -Zhenqiang diff --git a/gcc/cse.c b/gcc/cse.c index 852d13e..ce84982 100644 --- a/gcc/cse.c +++ b/gcc/cse.c @@ -4280,6 +4280,19 @@ find_sets_in_insn (rtx insn, struct set **psets) ; else if (GET_CODE (SET_SRC (y)) == CALL) ; + else if (GET_CODE (SET_SRC (y)) == ASM_OPERANDS) + { + if (i + 1 < lim) + { + rtx n = XVECEXP (x, 0, i + 1); + /* For inline assemble with multiple outputs, we can not + handle the SET separately. Refer PR60663. */ + if (GET_CODE (n) == SET + && GET_CODE (SET_SRC (n)) == ASM_OPERANDS) + break; + } + sets[n_sets++].rtl = y; + } else sets[n_sets++].rtl = y; }