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[209.132.180.131]) by mx.google.com with ESMTPS id gr2si14398727pac.283.2014.03.19.01.43.01 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 19 Mar 2014 01:43:01 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-363495-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 25600 invoked by alias); 19 Mar 2014 08:42:48 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 25586 invoked by uid 89); 19 Mar 2014 08:42:47 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-lb0-f169.google.com Received: from mail-lb0-f169.google.com (HELO mail-lb0-f169.google.com) (209.85.217.169) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Wed, 19 Mar 2014 08:42:41 +0000 Received: by mail-lb0-f169.google.com with SMTP id q8so5604824lbi.14 for ; Wed, 19 Mar 2014 01:42:37 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.112.221.227 with SMTP id qh3mr154465lbc.55.1395218557536; Wed, 19 Mar 2014 01:42:37 -0700 (PDT) Received: by 10.112.135.105 with HTTP; Wed, 19 Mar 2014 01:42:37 -0700 (PDT) Date: Wed, 19 Mar 2014 16:42:37 +0800 Message-ID: Subject: [PATCH, ARM] Fix ICE due to out of bound. From: Zhenqiang Chen To: "gcc-patches@gcc.gnu.org" Cc: Richard Earnshaw , Ramana Radhakrishnan X-IsSubscribed: yes X-Original-Sender: zhenqiang.chen@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 2607:f8b0:400c:c01::22c is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 Hi, ICE when compiling gcc.target/arm/neon-modes-3.c with "-g" in arm_dwarf_register_span since parts[8] is out of bound for XImode. GET_MODE_SIZE (XImode) / 4 is 16. "rtx parts[8]" can not hold all the registers. According to arm-modes.def, 16 should be the biggest number. So the patch updates parts to rtx parts[16]; Bootstrap and no make check regression on ARM Chrome book. OK for trunk? Thanks! -Zhenqiang ChangeLog: 2014-03-19 Zhenqiang Chen * config/arm/arm.c (arm_dwarf_register_span): Update the element number of parts. testsuite/ChangeLog: 2014-03-19 Zhenqiang Chen * gcc.target/arm/neon-modes-3.c: Add "-g" option. diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index a68ed8d..c4466c1 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -28692,7 +28692,7 @@ arm_dwarf_register_span (rtx rtl) { enum machine_mode mode; unsigned regno; - rtx parts[8]; + rtx parts[16]; int nregs; int i; diff --git a/gcc/testsuite/gcc.target/arm/neon-modes-3.c b/gcc/testsuite/gcc.target/arm/neon-modes-3.c index fe81875..f3e4f33 100644 --- a/gcc/testsuite/gcc.target/arm/neon-modes-3.c +++ b/gcc/testsuite/gcc.target/arm/neon-modes-3.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-require-effective-target arm_neon_ok } */ -/* { dg-options "-O" } */ +/* { dg-options "-O -g" } */ /* { dg-add-options arm_neon } */ #include