From patchwork Mon Jun 23 07:00:09 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhenqiang Chen X-Patchwork-Id: 32325 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-pa0-f69.google.com (mail-pa0-f69.google.com [209.85.220.69]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id A949E2055C for ; Mon, 23 Jun 2014 07:00:56 +0000 (UTC) Received: by mail-pa0-f69.google.com with SMTP id kq14sf25270127pab.4 for ; Mon, 23 Jun 2014 00:00:55 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:mailing-list:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:sender :delivered-to:mime-version:date:message-id:subject:from:to :x-original-sender:x-original-authentication-results:content-type; bh=muEMlWklHpkiihBdF8zLpfhZ2eqo5NNcBtKTpWRL5Yo=; b=hLfhJzlREu7sEPBFqJPQ6F9/ymN/dFA/P3Yz3fWbPrJvTHHlmD3UPEhY0BRhzcRulh ORDH9VBNds0m0fquk4l63yMy5IP96/or9DOC0XEZdh9FQjEfBln8t7da0HOUNFEGR+gp 66jKVo8U0oAyhPQbIZfeZDSsk0/REALpoEuQU42vEcsyds56oOcfzcQdPCjnge+6Tr7x YfNBPPYdvTc4KnJI2i8Viendp3yj3ydTg7u+xXBL3CMF/oiZUOYQLrZubjQKIJrmz50Q Qxp4hVBPfj7Kge6ztsSeGjqyBFNgvxHYSRkibzbz6Gi5k/P2XqWr/JkAzusGvVFbRKpt Clxw== X-Gm-Message-State: ALoCoQnpKjdY1NVtVNRT4iZuKBbqhoa6vKztO10FCzGwuNg97sbJW8cnzNvoZBQUWp6KXW+I3Z+O X-Received: by 10.68.202.99 with SMTP id kh3mr8851386pbc.8.1403506855902; Mon, 23 Jun 2014 00:00:55 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.32.203 with SMTP id h69ls1884318qgh.56.gmail; Mon, 23 Jun 2014 00:00:55 -0700 (PDT) X-Received: by 10.220.166.9 with SMTP id k9mr17709184vcy.20.1403506855799; Mon, 23 Jun 2014 00:00:55 -0700 (PDT) Received: from mail-ve0-x235.google.com (mail-ve0-x235.google.com [2607:f8b0:400c:c01::235]) by mx.google.com with ESMTPS id o2si3071497vca.94.2014.06.23.00.00.55 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 23 Jun 2014 00:00:55 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2607:f8b0:400c:c01::235 as permitted sender) client-ip=2607:f8b0:400c:c01::235; Received: by mail-ve0-f181.google.com with SMTP id db11so5599956veb.26 for ; Mon, 23 Jun 2014 00:00:55 -0700 (PDT) X-Received: by 10.52.30.9 with SMTP id o9mr4278462vdh.15.1403506855673; Mon, 23 Jun 2014 00:00:55 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.221.37.5 with SMTP id tc5csp109996vcb; Mon, 23 Jun 2014 00:00:55 -0700 (PDT) X-Received: by 10.66.141.165 with SMTP id rp5mr26408007pab.90.1403506854960; Mon, 23 Jun 2014 00:00:54 -0700 (PDT) Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id xo10si20555970pac.162.2014.06.23.00.00.54 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 23 Jun 2014 00:00:54 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-370791-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 15215 invoked by alias); 23 Jun 2014 07:00:42 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 15202 invoked by uid 89); 23 Jun 2014 07:00:41 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-lb0-f181.google.com Received: from mail-lb0-f181.google.com (HELO mail-lb0-f181.google.com) (209.85.217.181) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Mon, 23 Jun 2014 07:00:13 +0000 Received: by mail-lb0-f181.google.com with SMTP id p9so3809218lbv.26 for ; Mon, 23 Jun 2014 00:00:09 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.112.162.70 with SMTP id xy6mr15159749lbb.40.1403506809874; Mon, 23 Jun 2014 00:00:09 -0700 (PDT) Received: by 10.112.13.36 with HTTP; Mon, 23 Jun 2014 00:00:09 -0700 (PDT) Date: Mon, 23 Jun 2014 15:00:09 +0800 Message-ID: Subject: [PATCH, 6/10] aarch64: add ccmp CC mode From: Zhenqiang Chen To: "gcc-patches@gcc.gnu.org" X-IsSubscribed: yes X-Original-Sender: zhenqiang.chen@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2607:f8b0:400c:c01::235 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 Hi, The patches add a set of CC mode for AARCH64, which is similar as them for ARM. OK for trunk? Thanks! -Zhenqiang ChangeLog: 2014-06-23 Zhenqiang Chen * config/aarch64/aarch64-modes.def: Define new CC modes for ccmp. * config/aarch64/aarch64.c (aarch64_get_condition_code_1): New prototype. (aarch64_get_condition_code): Call aarch64_get_condition_code_1. (aarch64_get_condition_code_1): New function to handle ccmp CC mode. * config/aarch64/predicates.md (ccmp_cc_register): New. diff --git a/gcc/config/aarch64/aarch64-modes.def b/gcc/config/aarch64/aarch64-modes.def index 1d2cc76..71fd2f0 100644 --- a/gcc/config/aarch64/aarch64-modes.def +++ b/gcc/config/aarch64/aarch64-modes.def @@ -25,6 +25,16 @@ CC_MODE (CC_ZESWP); /* zero-extend LHS (but swap to make it RHS). */ CC_MODE (CC_SESWP); /* sign-extend LHS (but swap to make it RHS). */ CC_MODE (CC_NZ); /* Only N and Z bits of condition flags are valid. */ CC_MODE (CC_Z); /* Only Z bit of condition flags is valid. */ +CC_MODE (CC_DNE); +CC_MODE (CC_DEQ); +CC_MODE (CC_DLE); +CC_MODE (CC_DLT); +CC_MODE (CC_DGE); +CC_MODE (CC_DGT); +CC_MODE (CC_DLEU); +CC_MODE (CC_DLTU); +CC_MODE (CC_DGEU); +CC_MODE (CC_DGTU); /* Vector modes. */ VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI. */ diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index ecf88f9..e5ede6e 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -3460,6 +3460,9 @@ aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y) } static unsigned +aarch64_get_condition_code_1 (enum machine_mode, enum rtx_code); + +static unsigned aarch64_get_condition_code (rtx x) { enum machine_mode mode = GET_MODE (XEXP (x, 0)); @@ -3467,7 +3470,12 @@ aarch64_get_condition_code (rtx x) if (GET_MODE_CLASS (mode) != MODE_CC) mode = SELECT_CC_MODE (comp_code, XEXP (x, 0), XEXP (x, 1)); + return aarch64_get_condition_code_1 (mode, comp_code); +} +static unsigned +aarch64_get_condition_code_1 (enum machine_mode mode, enum rtx_code comp_code) +{ switch (mode) { case CCFPmode: @@ -3490,6 +3498,27 @@ aarch64_get_condition_code (rtx x) } break; + case CC_DNEmode: + return comp_code == NE ? AARCH64_NE : AARCH64_EQ; + case CC_DEQmode: + return comp_code == NE ? AARCH64_EQ : AARCH64_NE; + case CC_DGEmode: + return comp_code == NE ? AARCH64_GE : AARCH64_LT; + case CC_DLTmode: + return comp_code == NE ? AARCH64_LT : AARCH64_GE; + case CC_DGTmode: + return comp_code == NE ? AARCH64_GT : AARCH64_LE; + case CC_DLEmode: + return comp_code == NE ? AARCH64_LE : AARCH64_GT; + case CC_DGEUmode: + return comp_code == NE ? AARCH64_CS : AARCH64_CC; + case CC_DLTUmode: + return comp_code == NE ? AARCH64_CC : AARCH64_CS; + case CC_DGTUmode: + return comp_code == NE ? AARCH64_HI : AARCH64_LS; + case CC_DLEUmode: + return comp_code == NE ? AARCH64_LS : AARCH64_HI; + case CCmode: switch (comp_code) { diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md index dd35714..ab02fd0 100644 --- a/gcc/config/aarch64/predicates.md +++ b/gcc/config/aarch64/predicates.md @@ -39,6 +39,23 @@ (ior (match_operand 0 "register_operand") (match_operand 0 "aarch64_ccmp_immediate"))) +(define_special_predicate "ccmp_cc_register" + (and (match_code "reg") + (and (match_test "REGNO (op) == CC_REGNUM") + (ior (match_test "mode == GET_MODE (op)") + (match_test "mode == VOIDmode + && (GET_MODE (op) == CC_DNEmode + || GET_MODE (op) == CC_DEQmode + || GET_MODE (op) == CC_DLEmode + || GET_MODE (op) == CC_DLTmode + || GET_MODE (op) == CC_DGEmode + || GET_MODE (op) == CC_DGTmode + || GET_MODE (op) == CC_DLEUmode + || GET_MODE (op) == CC_DLTUmode + || GET_MODE (op) == CC_DGEUmode + || GET_MODE (op) == CC_DGTUmode)")))) +) + (define_predicate "aarch64_simd_register" (and (match_code "reg") (ior (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_LO_REGS")