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[209.132.180.131]) by mx.google.com with ESMTPS id tq1si20450460pbc.162.2014.06.23.00.00.20 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 23 Jun 2014 00:00:21 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-370790-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 13596 invoked by alias); 23 Jun 2014 07:00:08 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 13579 invoked by uid 89); 23 Jun 2014 07:00:07 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.5 required=5.0 tests=AWL, BAYES_00, LIKELY_SPAM_BODY, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=no version=3.3.2 X-HELO: mail-lb0-f177.google.com Received: from mail-lb0-f177.google.com (HELO mail-lb0-f177.google.com) (209.85.217.177) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Mon, 23 Jun 2014 06:59:39 +0000 Received: by mail-lb0-f177.google.com with SMTP id u10so3883084lbd.36 for ; Sun, 22 Jun 2014 23:59:35 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.152.198.39 with SMTP id iz7mr399087lac.67.1403506775722; Sun, 22 Jun 2014 23:59:35 -0700 (PDT) Received: by 10.112.13.36 with HTTP; Sun, 22 Jun 2014 23:59:35 -0700 (PDT) Date: Mon, 23 Jun 2014 14:59:35 +0800 Message-ID: Subject: [PATCH, 5/10] aarch64: add ccmp operand predicate From: Zhenqiang Chen To: "gcc-patches@gcc.gnu.org" X-IsSubscribed: yes X-Original-Sender: zhenqiang.chen@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2607:f8b0:400c:c01::22e as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 Hi, The patches defines ccmp operand predicate for AARCH64. OK for trunk? Thanks! -Zhenqiang ChangeLog: 2014-06-23 Zhenqiang Chen * config/aarch64/aarch64-protos.h (aarch64_uimm5): New prototype. * config/aarch64/constraints.md (Usn): Immediate for ccmn. * config/aarch64/predicates.md (aarch64_ccmp_immediate): New. (aarch64_ccmp_operand): New. * config/aarch64/aarch64.c (aarch64_uimm5): New function. diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index c4f75b3..997ff50 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -246,6 +246,8 @@ void aarch64_init_expanders (void); void aarch64_print_operand (FILE *, rtx, char); void aarch64_print_operand_address (FILE *, rtx); +bool aarch64_uimm5 (HOST_WIDE_INT); + /* Initialize builtins for SIMD intrinsics. */ void init_aarch64_simd_builtins (void); diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index f2968ff..ecf88f9 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -9566,6 +9566,13 @@ aarch64_expand_movmem (rtx *operands) return true; } +/* Return true if val can be encoded as a 5-bit unsigned immediate. */ +bool +aarch64_uimm5 (HOST_WIDE_INT val) +{ + return (val & (HOST_WIDE_INT) 0x1f) == val; +} + #undef TARGET_ADDRESS_COST #define TARGET_ADDRESS_COST aarch64_address_cost diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md index 807d0b1..bb6a8a1 100644 --- a/gcc/config/aarch64/constraints.md +++ b/gcc/config/aarch64/constraints.md @@ -89,6 +89,11 @@ (and (match_code "const_int") (match_test "(unsigned HOST_WIDE_INT) ival < 32"))) +(define_constraint "Usn" + "A constant that can be used with a CCMN operation (once negated)." + (and (match_code "const_int") + (match_test "aarch64_uimm5 (-ival)"))) + (define_constraint "Usd" "@internal A constraint that matches an immediate shift constant in DImode." diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md index 2702a3c..dd35714 100644 --- a/gcc/config/aarch64/predicates.md +++ b/gcc/config/aarch64/predicates.md @@ -30,6 +30,15 @@ (ior (match_code "symbol_ref") (match_operand 0 "register_operand"))) +(define_predicate "aarch64_ccmp_immediate" + (and (match_code "const_int") + (ior (match_test "aarch64_uimm5 (INTVAL (op))") + (match_test "aarch64_uimm5 (-INTVAL (op))")))) + +(define_predicate "aarch64_ccmp_operand" + (ior (match_operand 0 "register_operand") + (match_operand 0 "aarch64_ccmp_immediate"))) + (define_predicate "aarch64_simd_register" (and (match_code "reg") (ior (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_LO_REGS")