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[209.132.180.131]) by mx.google.com with ESMTPS id zc3si20450400pbc.176.2014.06.23.00.02.19 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 23 Jun 2014 00:02:20 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-370795-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 20910 invoked by alias); 23 Jun 2014 07:02:07 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 20886 invoked by uid 89); 23 Jun 2014 07:02:06 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-lb0-f169.google.com Received: from mail-lb0-f169.google.com (HELO mail-lb0-f169.google.com) (209.85.217.169) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Mon, 23 Jun 2014 07:01:38 +0000 Received: by mail-lb0-f169.google.com with SMTP id l4so3931580lbv.0 for ; Mon, 23 Jun 2014 00:01:34 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.152.8.104 with SMTP id q8mr15688477laa.13.1403506894636; Mon, 23 Jun 2014 00:01:34 -0700 (PDT) Received: by 10.112.13.36 with HTTP; Mon, 23 Jun 2014 00:01:34 -0700 (PDT) Date: Mon, 23 Jun 2014 15:01:34 +0800 Message-ID: Subject: [PATCH, 10/10] aarch64: Handle ccmp in ifcvt to make it work with cmov From: Zhenqiang Chen To: "gcc-patches@gcc.gnu.org" X-IsSubscribed: yes X-Original-Sender: zhenqiang.chen@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2607:f8b0:400c:c01::231 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 Hi, The patch enhances ifcvt to handle conditional compare instruction (ccmp) to make it work with cmov. For ccmp, ALLOW_CC_MODE is set to TRUE when calling canonicalize_condition. And the backend does not need to generate additional "compare (CC, 0)" for it. Bootstrap and no check regression on qemu. OK for trunk? Thanks! -Zhenqiang ChangeLog: 2014-06-23 Zhenqiang Chen * config/aarch64/aarch64.md (movcc): Handle ccmp_cc. * ifcvt.c: #include "ccmp.h". (struct noce_if_info): Add a new field ccmp_p. (noce_emit_cmove): Allow ccmp condition. (noce_get_alt_condition): Call canonicalize_condition with ccmp_p. (noce_get_condition): Set ALLOW_CC_MODE to TRUE for ccmp. (noce_process_if_block): Set ccmp_p for ccmp. testsuite/ChangeLog: 2014-06-23 Zhenqiang Chen * gcc.target/aarch64/ccmn-csel-1.c: New testcase. * gcc.target/aarch64/ccmn-csel-2.c: New testcase. * gcc.target/aarch64/ccmn-csel-3.c: New testcase. * gcc.target/aarch64/ccmp-csel-1.c: New testcase. * gcc.target/aarch64/ccmp-csel-2.c: New testcase. * gcc.target/aarch64/ccmp-csel-3.c: New testcase. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index fcc5559..82cc561 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -2459,15 +2459,19 @@ (match_operand:ALLI 3 "register_operand" "")))] "" { - rtx ccreg; enum rtx_code code = GET_CODE (operands[1]); if (code == UNEQ || code == LTGT) FAIL; - ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0), - XEXP (operands[1], 1)); - operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx); + if (!ccmp_cc_register (XEXP (operands[1], 0), + GET_MODE (XEXP (operands[1], 0)))) + { + rtx ccreg; + ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0), + XEXP (operands[1], 1)); + operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx); + } } ) diff --git a/gcc/ifcvt.c b/gcc/ifcvt.c index 2ca2278..8ee1266 100644 --- a/gcc/ifcvt.c +++ b/gcc/ifcvt.c @@ -43,6 +43,7 @@ #include "vec.h" #include "pointer-set.h" #include "dbgcnt.h" +#include "ccmp.h" #ifndef HAVE_conditional_move #define HAVE_conditional_move 0 @@ -786,6 +787,9 @@ struct noce_if_info /* Estimated cost of the particular branch instruction. */ int branch_cost; + + /* The COND is a conditional compare or not. */ + bool ccmp_p; }; static rtx noce_emit_store_flag (struct noce_if_info *, rtx, int, int); @@ -1407,9 +1411,16 @@ noce_emit_cmove (struct noce_if_info *if_info, rtx x, enum rtx_code code, end_sequence (); } - /* Don't even try if the comparison operands are weird. */ - if (! general_operand (cmp_a, GET_MODE (cmp_a)) - || ! general_operand (cmp_b, GET_MODE (cmp_b))) + /* Don't even try if the comparison operands are weird + except conditional compare. */ + if (if_info->ccmp_p) + { + if (!(GET_MODE_CLASS (GET_MODE (cmp_a)) == MODE_CC + || GET_MODE_CLASS (GET_MODE (cmp_b)) == MODE_CC)) + return NULL_RTX; + } + else if (! general_operand (cmp_a, GET_MODE (cmp_a)) + || ! general_operand (cmp_b, GET_MODE (cmp_b))) return NULL_RTX; #if HAVE_conditional_move @@ -1849,7 +1860,7 @@ noce_get_alt_condition (struct noce_if_info *if_info, rtx target, } cond = canonicalize_condition (if_info->jump, cond, reverse, - earliest, target, false, true); + earliest, target, if_info->ccmp_p, true); if (! cond || ! reg_mentioned_p (target, cond)) return NULL; @@ -2300,6 +2311,7 @@ noce_get_condition (rtx jump, rtx *earliest, bool then_else_reversed) { rtx cond, set, tmp; bool reverse; + int allow_cc_mode = false; if (! any_condjump_p (jump)) return NULL_RTX; @@ -2333,10 +2345,21 @@ noce_get_condition (rtx jump, rtx *earliest, bool then_else_reversed) return cond; } + /* For conditional compare, set ALLOW_CC_MODE to TRUE. */ + if (targetm.gen_ccmp_first) + { + rtx prev = prev_nonnote_nondebug_insn (jump); + if (prev + && NONJUMP_INSN_P (prev) + && BLOCK_FOR_INSN (prev) == BLOCK_FOR_INSN (jump) + && ccmp_insn_p (prev)) + allow_cc_mode = true; + } + /* Otherwise, fall back on canonicalize_condition to do the dirty work of manipulating MODE_CC values and COMPARE rtx codes. */ tmp = canonicalize_condition (jump, cond, reverse, earliest, - NULL_RTX, false, true); + NULL_RTX, allow_cc_mode, true); /* We don't handle side-effects in the condition, like handling REG_INC notes and making sure no duplicate conditions are emitted. */ @@ -2577,6 +2600,11 @@ noce_process_if_block (struct noce_if_info *if_info) if_info->a = a; if_info->b = b; + if (targetm.gen_ccmp_first) + if (GET_MODE_CLASS (GET_MODE (XEXP (if_info->cond, 0))) == MODE_CC + || GET_MODE_CLASS (GET_MODE (XEXP (if_info->cond, 1))) == MODE_CC) + if_info->ccmp_p = true; + /* Try optimizations in some approximation of a useful order. */ /* ??? Should first look to see if X is live incoming at all. If it isn't, we don't need anything but an unconditional set. */ diff --git a/gcc/testsuite/gcc.target/aarch64/ccmn-csel-1.c b/gcc/testsuite/gcc.target/aarch64/ccmn-csel-1.c new file mode 100644 index 0000000..472c271 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ccmn-csel-1.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options " -O2 " } */ + +int foo (int a, int b, int c, int d) +{ + return a < b && c > -5 ? d : 7; +} + +/* { dg-final { scan-assembler "ccmn" } } */ +/* { dg-final { scan-assembler "csel" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/ccmn-csel-2.c b/gcc/testsuite/gcc.target/aarch64/ccmn-csel-2.c new file mode 100644 index 0000000..c7d41d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ccmn-csel-2.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options " -O2 " } */ + +int foo (int a, int b, int c, int d) +{ + return a < b && c > -9 ? d : c; +} + +/* { dg-final { scan-assembler "ccmn" } } */ +/* { dg-final { scan-assembler "csel" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/ccmn-csel-3.c b/gcc/testsuite/gcc.target/aarch64/ccmn-csel-3.c new file mode 100644 index 0000000..9350e5d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ccmn-csel-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options " -O2 " } */ + +int foo (int a, int b, int c, int d) +{ + return a > b && c <= -2 ? 9 : 7; +} + +/* { dg-final { scan-assembler "ccmn" } } */ +/* { dg-final { scan-assembler "csel" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/ccmp-csel-1.c b/gcc/testsuite/gcc.target/aarch64/ccmp-csel-1.c new file mode 100644 index 0000000..2d0929f --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ccmp-csel-1.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options " -O2 " } */ + +int foo (int a, int b, int c, int d) +{ + return a < b && c <= d ? d : 7; +} + +/* { dg-final { scan-assembler "ccmp" } } */ +/* { dg-final { scan-assembler "csel" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/ccmp-csel-2.c b/gcc/testsuite/gcc.target/aarch64/ccmp-csel-2.c new file mode 100644 index 0000000..978aa64 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ccmp-csel-2.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options " -O2 " } */ + +int foo (int a, int b, int c, int d) +{ + return a < b && c > d ? d : c; +} + +/* { dg-final { scan-assembler "ccmp" } } */ +/* { dg-final { scan-assembler "csel" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/ccmp-csel-3.c b/gcc/testsuite/gcc.target/aarch64/ccmp-csel-3.c new file mode 100644 index 0000000..7db1cd5 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ccmp-csel-3.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options " -O2 " } */ + +int foo (int a, int b, int c, int d) +{ + return a > b && c <= d ? 9 : 7; +} + +/* { dg-final { scan-assembler "ccmp" } } */ +/* { dg-final { scan-assembler "csel" } } */