From patchwork Tue Jul 24 12:09:21 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramana Radhakrishnan X-Patchwork-Id: 10225 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 0FCB423E57 for ; Tue, 24 Jul 2012 12:09:28 +0000 (UTC) Received: from mail-gh0-f180.google.com (mail-gh0-f180.google.com [209.85.160.180]) by fiordland.canonical.com (Postfix) with ESMTP id 97D7AA19B5D for ; Tue, 24 Jul 2012 12:09:27 +0000 (UTC) Received: by ghbz12 with SMTP id z12so6863321ghb.11 for ; Tue, 24 Jul 2012 05:09:27 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf :mime-version:date:message-id:subject:from:to:cc:content-type :x-gm-message-state; bh=mc/VdA76+sWEm1H3uMwGkTKHQ7VSjG7RL8RUJkbVZ08=; b=oLpDK+/NgSCC4EBH6p5s+igv5NxqfNzoEa5YYOo+wBRHZqMyXLPICTbMbjlq2G5tEQ k654CllsdzbUenCavR7eu5D4aNO4BxvqQFZneNTpUuYyVU10Mx6w7Sd8eQLji6o4Z1mT N1elm1yu26F1lMxrItZdKajW/s6qHHUJlabiYPO+yn6jNHXBK29lliAvd2xk3Em4synK lgj+bDt0XbScChe+6P9x21whi7+JXs2zJD2F2JFNuAFHwNFkISpmEW/w/e8Q+AhowpRu /jNDzjN+h2arkGMLuDLw7LChpWbwFNDdSkeOhZ1UKhe6t2jdRhfMCLGfJgyigztM4KVu 8x1A== Received: by 10.43.69.12 with SMTP id ya12mr14952994icb.50.1343131762607; Tue, 24 Jul 2012 05:09:22 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.153.7 with SMTP id i7csp71512ibw; Tue, 24 Jul 2012 05:09:21 -0700 (PDT) Received: by 10.220.116.6 with SMTP id k6mr15408422vcq.59.1343131761692; Tue, 24 Jul 2012 05:09:21 -0700 (PDT) Received: from mail-vc0-f178.google.com (mail-vc0-f178.google.com [209.85.220.178]) by mx.google.com with ESMTPS id nk19si4412491vcb.40.2012.07.24.05.09.21 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 24 Jul 2012 05:09:21 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.220.178 is neither permitted nor denied by best guess record for domain of ramana.radhakrishnan@linaro.org) client-ip=209.85.220.178; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.178 is neither permitted nor denied by best guess record for domain of ramana.radhakrishnan@linaro.org) smtp.mail=ramana.radhakrishnan@linaro.org Received: by vcbf13 with SMTP id f13so7158090vcb.37 for ; Tue, 24 Jul 2012 05:09:21 -0700 (PDT) MIME-Version: 1.0 Received: by 10.52.19.133 with SMTP id f5mr13443225vde.41.1343131761245; Tue, 24 Jul 2012 05:09:21 -0700 (PDT) Received: by 10.58.222.10 with HTTP; Tue, 24 Jul 2012 05:09:21 -0700 (PDT) Date: Tue, 24 Jul 2012 13:09:21 +0100 Message-ID: Subject: [PR 54051 ARM] Fix alignment specifier alignment information for ARM. From: Ramana Radhakrishnan To: gcc-patches Cc: Patch Tracking X-Gm-Message-State: ALoCoQm753o5D9CEe01BoQFBnU4r1Gb+5z+Hssrgj2K9VdBk1Q9YeddnVq4Sp+ERdzVrIhdGxeIB Hi , While testing my neon intrinsics work with some testcases that I was writing up, I ran into PR54051 . The one change which is probably a bit long standing is the fact that for register only addressing modes i.e. something like mem (reg:SI) we were printing out addresses with an immediate of #0. Historically the reason for this appears to be to deal with an assembler bug of yesteryears where the assembler couldn't sometimes properly distinguish between auto-inc addressing forms and the register indirect addressing form which I'm informed is fixed. This patch has gone through a full test run with qemu in a cross environment with no regressions for armv7-a / neon / arm/ thumb with a v5t multilib for c, c++ . I intend to backport this to 4.7 as this is a regression compared to 4.6, after letting it be on trunk for a few days to see if the auto-testers pick anything else up unless there is an objection from anyone. regards Ramana PR target/54051 * config/arm/arm.c (arm_print_operand_address): Remove superfluous printing of #0. * config/arm/neon.md ("neon_vld3_lane":VD): Remove alignment specifier. ("neon_vld3_lane":VMQ): Likewise. ("neon_vld3_dup":VDX): Likewise. ("neon_vst3_lane":VD): Likewise. ("neon_vst3_lane":VMQ): Likewise. PR target/54051 * gcc.target/arm/pr54051.c: New. * gcc.target/arm/vfp-1.c: Adjust test. Index: gcc/testsuite/gcc.target/arm/pr54051.c =================================================================== --- gcc/testsuite/gcc.target/arm/pr54051.c (revision 0) +++ gcc/testsuite/gcc.target/arm/pr54051.c (revision 189808) @@ -0,0 +1,20 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +#include + +int32_t a __attribute__ ((aligned (64))); + +int32x2x3_t test (void) +{ + return vld3_dup_s32 (&a); +} + +int32x2x3_t test1 (void) +{ + int32x2x3_t res ; + return vld3_lane_s32 (&a, res, 1); +} + Index: gcc/testsuite/gcc.target/arm/vfp-1.c =================================================================== --- gcc/testsuite/gcc.target/arm/vfp-1.c (revision 189807) +++ gcc/testsuite/gcc.target/arm/vfp-1.c (revision 189808) @@ -129,7 +129,7 @@ /* { dg-final { scan-assembler "flds.+ \\\[r0, #1020\\\]" } } */ /* { dg-final { scan-assembler "flds.+ \\\[r\[0-9\], #-1020\\\]" { target { arm32 && { ! arm_thumb2_ok } } } } } */ /* { dg-final { scan-assembler "add.+ r0, #1024" } } */ - /* { dg-final { scan-assembler "fsts.+ \\\[r\[0-9\], #0\\\]\n" } } */ + /* { dg-final { scan-assembler "fsts.+ \\\[r\[0-9\]\\\]\n" } } */ f[256] = f[255] + f[-255]; /* { dg-final { scan-assembler "fldd.+ \\\[r1, #1016\\\]" } } */ Index: gcc/config/arm/arm.c =================================================================== --- gcc/config/arm/arm.c (revision 189807) +++ gcc/config/arm/arm.c (revision 189808) @@ -17420,7 +17420,7 @@ int is_minus = GET_CODE (x) == MINUS; if (GET_CODE (x) == REG) - asm_fprintf (stream, "[%r, #0]", REGNO (x)); + asm_fprintf (stream, "[%r]", REGNO (x)); else if (GET_CODE (x) == PLUS || is_minus) { rtx base = XEXP (x, 0); Index: gcc/config/arm/neon.md =================================================================== --- gcc/config/arm/neon.md (revision 189807) +++ gcc/config/arm/neon.md (revision 189808) @@ -4806,7 +4806,7 @@ ops[2] = gen_rtx_REG (DImode, regno + 4); ops[3] = operands[1]; ops[4] = operands[3]; - output_asm_insn ("vld3.\t{%P0[%c4], %P1[%c4], %P2[%c4]}, %A3", + output_asm_insn ("vld3.\t{%P0[%c4], %P1[%c4], %P2[%c4]}, %3", ops); return ""; } @@ -4838,7 +4838,7 @@ ops[2] = gen_rtx_REG (DImode, regno + 8); ops[3] = operands[1]; ops[4] = GEN_INT (lane); - output_asm_insn ("vld3.\t{%P0[%c4], %P1[%c4], %P2[%c4]}, %A3", + output_asm_insn ("vld3.\t{%P0[%c4], %P1[%c4], %P2[%c4]}, %3", ops); return ""; } @@ -4860,7 +4860,7 @@ ops[1] = gen_rtx_REG (DImode, regno + 2); ops[2] = gen_rtx_REG (DImode, regno + 4); ops[3] = operands[1]; - output_asm_insn ("vld3.\t{%P0[], %P1[], %P2[]}, %A3", ops); + output_asm_insn ("vld3.\t{%P0[], %P1[], %P2[]}, %3", ops); return ""; } else @@ -4978,7 +4978,7 @@ ops[2] = gen_rtx_REG (DImode, regno + 2); ops[3] = gen_rtx_REG (DImode, regno + 4); ops[4] = operands[2]; - output_asm_insn ("vst3.\t{%P1[%c4], %P2[%c4], %P3[%c4]}, %A0", + output_asm_insn ("vst3.\t{%P1[%c4], %P2[%c4], %P3[%c4]}, %0", ops); return ""; } @@ -5010,7 +5010,7 @@ ops[2] = gen_rtx_REG (DImode, regno + 4); ops[3] = gen_rtx_REG (DImode, regno + 8); ops[4] = GEN_INT (lane); - output_asm_insn ("vst3.\t{%P1[%c4], %P2[%c4], %P3[%c4]}, %A0", + output_asm_insn ("vst3.\t{%P1[%c4], %P2[%c4], %P3[%c4]}, %0", ops); return ""; }