From patchwork Tue Mar 27 13:17:01 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramana Radhakrishnan X-Patchwork-Id: 7482 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id C496B23E0E for ; Tue, 27 Mar 2012 13:17:03 +0000 (UTC) Received: from mail-gy0-f180.google.com (mail-gy0-f180.google.com [209.85.160.180]) by fiordland.canonical.com (Postfix) with ESMTP id 79A82A1885E for ; Tue, 27 Mar 2012 13:17:03 +0000 (UTC) Received: by ghbz12 with SMTP id z12so5628797ghb.11 for ; Tue, 27 Mar 2012 06:17:03 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf :mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:x-gm-message-state; bh=kDzoDPZRHgVfkcOjo4RJPTCRLpchTV8Jwa/0bxUfBZA=; b=PVb1SEGxqoOefM4JZpt5zkjQ2gZ6wkPx24DtCt/YWA6py4h/MssyhhRgJmBqmWI7or uUtijXlgdvSj5pcCH51ZrTdApJtGjRHyWqngffw/gl5bE0FZesr8nxwQawKp048zAATv SQ7fglqZbfAVAqsJvybsIz/79pxkqQ57C4LujL917tCaCsXb/a7YFgyvLy6YPoTy1qUM lKawM3T6JDxZx60cdJKRz2Ii2FVqGCpfAvDkou5JdGtVFtcZxbcdRSX5eqEVMAVDrXJb cAdsvAfIzWOkuTekwhd2WtfLyfIxSBhMmf5U1wZ1oEK/cNwjuXya7KprtA+ngOodoG8r 44jw== Received: by 10.50.46.195 with SMTP id x3mr8683722igm.54.1332854222766; Tue, 27 Mar 2012 06:17:02 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.5.205 with SMTP id 13csp17239ibw; Tue, 27 Mar 2012 06:17:01 -0700 (PDT) Received: by 10.224.59.204 with SMTP id m12mr32802216qah.37.1332854221467; Tue, 27 Mar 2012 06:17:01 -0700 (PDT) Received: from mail-qa0-f43.google.com (mail-qa0-f43.google.com [209.85.216.43]) by mx.google.com with ESMTPS id n1si7834919qcv.181.2012.03.27.06.17.01 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 27 Mar 2012 06:17:01 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.216.43 is neither permitted nor denied by best guess record for domain of ramana.radhakrishnan@linaro.org) client-ip=209.85.216.43; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.216.43 is neither permitted nor denied by best guess record for domain of ramana.radhakrishnan@linaro.org) smtp.mail=ramana.radhakrishnan@linaro.org Received: by qadb15 with SMTP id b15so3838556qad.16 for ; Tue, 27 Mar 2012 06:17:01 -0700 (PDT) MIME-Version: 1.0 Received: by 10.224.77.80 with SMTP id f16mr33130683qak.10.1332854221136; Tue, 27 Mar 2012 06:17:01 -0700 (PDT) Received: by 10.224.95.196 with HTTP; Tue, 27 Mar 2012 06:17:01 -0700 (PDT) In-Reply-To: References: Date: Tue, 27 Mar 2012 14:17:01 +0100 Message-ID: Subject: Re: [RFC ivopts] ARM - Make ivopts take into account whether pre and post increments are actually supported on targets. From: Ramana Radhakrishnan To: gcc-patches Cc: Patch Tracking X-Gm-Message-State: ALoCoQl6yg8m/f3y6AhWr1diWfbyu5hQHrA+VqANi5fHLYQkH7rN6aHArM+g9kHVIBHeEPgWl4yD And the patch is now attached .... Ramana diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index 900d09a..6e82fb0 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -247,5 +247,5 @@ extern int vfp3_const_double_for_fract_bits (rtx); extern void arm_expand_vec_perm (rtx target, rtx op0, rtx op1, rtx sel); extern bool arm_expand_vec_perm_const (rtx target, rtx op0, rtx op1, rtx sel); - +extern bool arm_autoinc_modes_ok_p (enum machine_mode, int); #endif /* ! GCC_ARM_PROTOS_H */ diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 9af66dd..31d6d9f 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -25652,5 +25652,40 @@ arm_vectorize_vec_perm_const_ok (enum machine_mode vmode, return ret; } +bool +arm_autoinc_modes_ok_p (enum machine_mode mode, int code) +{ + if (TARGET_SOFT_FLOAT) + return true; + + switch (code) + { + case ARM_POST_INC: + case ARM_PRE_DEC: + if (VECTOR_MODE_P (mode)) + { + if (code != PRE_DEC) + return true; + else + return false; + } + + return true; + + case ARM_POST_DEC: + case ARM_PRE_INC: + if (FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode)) + return false; + else + return true; + + default: + return false; + + } + + return false; +} + #include "gt-arm.h" diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 443d2ed..2e4f3a0 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -1623,6 +1623,27 @@ typedef struct #define HAVE_PRE_MODIFY_REG TARGET_32BIT #define HAVE_POST_MODIFY_REG TARGET_32BIT +#define ARM_POST_INC 0 +#define ARM_PRE_INC 1 +#define ARM_POST_DEC 2 +#define ARM_PRE_DEC 3 + +#define ARM_AUTOINC_VALID_FOR_MODE_P(mode, code) \ + (TARGET_32BIT && arm_autoinc_modes_ok_p (mode, code)) +#define USE_LOAD_POST_INCREMENT(mode) \ + ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_INC) +#define USE_LOAD_PRE_INCREMENT(mode) \ + ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_INC) +#define USE_LOAD_POST_DECREMENT(mode) \ + ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_DEC) +#define USE_LOAD_PRE_DECREMENT(mode) \ + ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_DEC) + +#define USE_STORE_PRE_DECREMENT(mode) USE_LOAD_PRE_DECREMENT(mode) +#define USE_STORE_PRE_INCREMENT(mode) USE_LOAD_PRE_INCREMENT(mode) +#define USE_STORE_POST_DECREMENT(mode) USE_LOAD_POST_DECREMENT(mode) +#define USE_STORE_POST_INCREMENT(mode) USE_LOAD_POST_INCREMENT(mode) + /* Macros to check register numbers against specific register classes. */ /* These assume that REGNO is a hard or pseudo reg number. diff --git a/gcc/tree-ssa-loop-ivopts.c b/gcc/tree-ssa-loop-ivopts.c index 527c911..ac37608 100644 --- a/gcc/tree-ssa-loop-ivopts.c +++ b/gcc/tree-ssa-loop-ivopts.c @@ -2361,8 +2361,12 @@ add_autoinc_candidates (struct ivopts_data *data, tree base, tree step, cstepi = int_cst_value (step); mem_mode = TYPE_MODE (TREE_TYPE (*use->op_p)); - if ((HAVE_PRE_INCREMENT && GET_MODE_SIZE (mem_mode) == cstepi) - || (HAVE_PRE_DECREMENT && GET_MODE_SIZE (mem_mode) == -cstepi)) + if (((USE_LOAD_PRE_INCREMENT (mem_mode) + || USE_STORE_PRE_INCREMENT (mem_mode)) + && GET_MODE_SIZE (mem_mode) == cstepi) + || ((USE_LOAD_PRE_DECREMENT (mem_mode) + || USE_STORE_PRE_DECREMENT (mem_mode)) + && GET_MODE_SIZE (mem_mode) == -cstepi)) { enum tree_code code = MINUS_EXPR; tree new_base; @@ -2379,8 +2383,12 @@ add_autoinc_candidates (struct ivopts_data *data, tree base, tree step, add_candidate_1 (data, new_base, step, important, IP_BEFORE_USE, use, use->stmt); } - if ((HAVE_POST_INCREMENT && GET_MODE_SIZE (mem_mode) == cstepi) - || (HAVE_POST_DECREMENT && GET_MODE_SIZE (mem_mode) == -cstepi)) + if (((USE_LOAD_POST_INCREMENT (mem_mode) + || USE_STORE_POST_INCREMENT (mem_mode)) + && GET_MODE_SIZE (mem_mode) == cstepi) + || ((USE_LOAD_POST_DECREMENT (mem_mode) + || USE_STORE_POST_DECREMENT (mem_mode)) + && GET_MODE_SIZE (mem_mode) == -cstepi)) { add_candidate_1 (data, base, step, important, IP_AFTER_USE, use, use->stmt); @@ -3314,25 +3322,29 @@ get_address_cost (bool symbol_present, bool var_present, reg0 = gen_raw_REG (address_mode, LAST_VIRTUAL_REGISTER + 1); reg1 = gen_raw_REG (address_mode, LAST_VIRTUAL_REGISTER + 2); - if (HAVE_PRE_DECREMENT) + if (USE_LOAD_PRE_DECREMENT (mem_mode) + || USE_STORE_PRE_DECREMENT (mem_mode)) { addr = gen_rtx_PRE_DEC (address_mode, reg0); has_predec[mem_mode] = memory_address_addr_space_p (mem_mode, addr, as); } - if (HAVE_POST_DECREMENT) + if (USE_LOAD_POST_DECREMENT (mem_mode) + || USE_STORE_POST_DECREMENT (mem_mode)) { addr = gen_rtx_POST_DEC (address_mode, reg0); has_postdec[mem_mode] = memory_address_addr_space_p (mem_mode, addr, as); } - if (HAVE_PRE_INCREMENT) + if (USE_LOAD_PRE_INCREMENT (mem_mode) + || USE_STORE_PRE_DECREMENT (mem_mode)) { addr = gen_rtx_PRE_INC (address_mode, reg0); has_preinc[mem_mode] = memory_address_addr_space_p (mem_mode, addr, as); } - if (HAVE_POST_INCREMENT) + if (USE_LOAD_POST_INCREMENT (mem_mode) + || USE_STORE_POST_INCREMENT (mem_mode)) { addr = gen_rtx_POST_INC (address_mode, reg0); has_postinc[mem_mode]