From patchwork Tue Aug 14 15:01:44 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramana Radhakrishnan X-Patchwork-Id: 10729 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 2BE5623E53 for ; Tue, 14 Aug 2012 15:01:47 +0000 (UTC) Received: from mail-yw0-f52.google.com (mail-yw0-f52.google.com [209.85.213.52]) by fiordland.canonical.com (Postfix) with ESMTP id D0FC1A182A9 for ; Tue, 14 Aug 2012 15:01:46 +0000 (UTC) Received: by yhpp61 with SMTP id p61so568341yhp.11 for ; Tue, 14 Aug 2012 08:01:46 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf :mime-version:date:message-id:subject:from:to:cc:content-type :x-gm-message-state; bh=iMd3kZySx1JsSouZjTStTibi2nJb5QbuQRyDG/AOLRI=; b=f1GVLKWegcSev57EJi9r62mqbwuoSYMZWBBAuHn/dUeeLUMMRdBuqjtA+/iBT4dAOs 6lv6PJjmG/6EvubsjrSRlFS9CnD/QPYqT/jamAWcpT7ue2yS+Z1WpiTS1EBBYnr6aoTu qfh41FL4e1UMGe+CD0n4+ed0OvZUXKgKiIJ8UUY8c6NMToAxPcT1Wl9plsFK037UVdUR 69uye2fR90Z8B1yhvSUyUVvzdJpZrUT9ipTYAGwJrI/32UYW3a2MuLHvYMYP6wzgR4GY lR5VzGNpF7GPUdIMDJV6PQCfauybBSQxqUAEF3Tk/sLoKBTlhfMxgAN0qcmZ9JLJ+E9y b6gQ== Received: by 10.50.170.3 with SMTP id ai3mr355928igc.9.1344956506124; Tue, 14 Aug 2012 08:01:46 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.184.200 with SMTP id ew8csp18436igc; Tue, 14 Aug 2012 08:01:45 -0700 (PDT) Received: by 10.220.152.67 with SMTP id f3mr10895563vcw.19.1344956505266; Tue, 14 Aug 2012 08:01:45 -0700 (PDT) Received: from mail-vc0-f178.google.com (mail-vc0-f178.google.com [209.85.220.178]) by mx.google.com with ESMTPS id v12si1456821vcw.43.2012.08.14.08.01.44 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 14 Aug 2012 08:01:45 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.220.178 is neither permitted nor denied by best guess record for domain of ramana.radhakrishnan@linaro.org) client-ip=209.85.220.178; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.178 is neither permitted nor denied by best guess record for domain of ramana.radhakrishnan@linaro.org) smtp.mail=ramana.radhakrishnan@linaro.org Received: by vcbf13 with SMTP id f13so569561vcb.37 for ; Tue, 14 Aug 2012 08:01:44 -0700 (PDT) MIME-Version: 1.0 Received: by 10.52.97.196 with SMTP id ec4mr9390849vdb.96.1344956504444; Tue, 14 Aug 2012 08:01:44 -0700 (PDT) Received: by 10.58.187.170 with HTTP; Tue, 14 Aug 2012 08:01:44 -0700 (PDT) Date: Tue, 14 Aug 2012 16:01:44 +0100 Message-ID: Subject: [Patch ARM] Fix PR54212 - Remove predicable attribute from Advanced SIMD patterns in the ARM backend. From: Ramana Radhakrishnan To: gcc-patches Cc: Patch Tracking X-Gm-Message-State: ALoCoQlbN+bK4KdkuBpO/7ZVeeuCw+KBdtzxvuO2PZGd4UdkyCFe6GwS7VXhE308IHHgAsF4qd+V Hi, This fixes PR target/54212.. The problem here was we were marking a number of patterns in neon.md as predicable. Advanced SIMD instructions are not predicable in ARM state, however are allowed to exist in Thumb2 in IT blocks ( though this is a feature that is deprecated and is documented in the latest ARM ARM Issue C.B ) . This therefore removes the predicable attribute from all such instructions in the Neon backend. This is currently undergoing regression testing on armv7-a cross, will apply if no regressions and I intend backporting this atleast to 4.7 branch as this is an issue in the backend since the original days of Advanced SIMD support and the bug report was reported on the 4.7 branch where it is reproducible. I would like to take this back to 4.6 branch as well but would like to do so after it has lived for a while on trunk / 4.7 . regards, Ramana 2012-08-14 Ramana Radhakrishnan PR target/54212 * config/arm/neon.md (vec_set_internal VD,VQ): Do not mark as predicable. Adjust asm template. (vec_setv2di_internal): Likewise. (vec_extract VD, VQ): Likewise. (vec_extractv2di): Likewise. (neon_vget_lane_sext_internal VD, VQ): Likewise. (neon_vset_lane_sext_internal VD, VQ): Likewise. (neon_vdup_n VX, V32): Likewise. (neon_vdup_nv2di): Likewise. diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 7142c98..12c7934 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -434,10 +434,9 @@ elt = GET_MODE_NUNITS (mode) - 1 - elt; operands[2] = GEN_INT (elt); - return "vmov%?.\t%P0[%c2], %1"; + return "vmov.\t%P0[%c2], %1"; } - [(set_attr "predicable" "yes") - (set_attr "neon_type" "neon_mcr")]) + [(set_attr "neon_type" "neon_mcr")]) (define_insn "vec_set_internal" [(set (match_operand:VQ 0 "s_register_operand" "=w") @@ -460,10 +459,9 @@ operands[0] = gen_rtx_REG (mode, regno + hi); operands[2] = GEN_INT (elt); - return "vmov%?.\t%P0[%c2], %1"; + return "vmov.\t%P0[%c2], %1"; } - [(set_attr "predicable" "yes") - (set_attr "neon_type" "neon_mcr")] + [(set_attr "neon_type" "neon_mcr")] ) (define_insn "vec_setv2di_internal" @@ -480,10 +478,9 @@ operands[0] = gen_rtx_REG (DImode, regno); - return "vmov%?\t%P0, %Q1, %R1"; + return "vmov\t%P0, %Q1, %R1"; } - [(set_attr "predicable" "yes") - (set_attr "neon_type" "neon_mcr_2_mcrr")] + [(set_attr "neon_type" "neon_mcr_2_mcrr")] ) (define_expand "vec_set" @@ -511,10 +508,9 @@ elt = GET_MODE_NUNITS (mode) - 1 - elt; operands[2] = GEN_INT (elt); } - return "vmov%?.\t%0, %P1[%c2]"; + return "vmov.\t%0, %P1[%c2]"; } - [(set_attr "predicable" "yes") - (set_attr "neon_type" "neon_bp_simple")] + [(set_attr "neon_type" "neon_bp_simple")] ) (define_insn "vec_extract" @@ -535,10 +531,9 @@ operands[1] = gen_rtx_REG (mode, regno + hi); operands[2] = GEN_INT (elt); - return "vmov%?.\t%0, %P1[%c2]"; + return "vmov.\t%0, %P1[%c2]"; } - [(set_attr "predicable" "yes") - (set_attr "neon_type" "neon_bp_simple")] + [(set_attr "neon_type" "neon_bp_simple")] ) (define_insn "vec_extractv2di" @@ -552,10 +547,9 @@ operands[1] = gen_rtx_REG (DImode, regno); - return "vmov%?\t%Q0, %R0, %P1 @ v2di"; + return "vmov\t%Q0, %R0, %P1 @ v2di"; } - [(set_attr "predicable" "yes") - (set_attr "neon_type" "neon_int_1")] + [(set_attr "neon_type" "neon_int_1")] ) (define_expand "vec_init" @@ -2622,10 +2616,9 @@ elt = GET_MODE_NUNITS (mode) - 1 - elt; operands[2] = GEN_INT (elt); } - return "vmov%?.s\t%0, %P1[%c2]"; + return "vmov.s\t%0, %P1[%c2]"; } - [(set_attr "predicable" "yes") - (set_attr "neon_type" "neon_bp_simple")] + [(set_attr "neon_type" "neon_bp_simple")] ) (define_insn "neon_vget_lane_zext_internal" @@ -2642,10 +2635,9 @@ elt = GET_MODE_NUNITS (mode) - 1 - elt; operands[2] = GEN_INT (elt); } - return "vmov%?.u\t%0, %P1[%c2]"; + return "vmov.u\t%0, %P1[%c2]"; } - [(set_attr "predicable" "yes") - (set_attr "neon_type" "neon_bp_simple")] + [(set_attr "neon_type" "neon_bp_simple")] ) (define_insn "neon_vget_lane_sext_internal" @@ -2668,12 +2660,11 @@ ops[0] = operands[0]; ops[1] = gen_rtx_REG (mode, regno + 2 * (elt / halfelts)); ops[2] = GEN_INT (elt_adj); - output_asm_insn ("vmov%?.s\t%0, %P1[%c2]", ops); + output_asm_insn ("vmov.s\t%0, %P1[%c2]", ops); return ""; } - [(set_attr "predicable" "yes") - (set_attr "neon_type" "neon_bp_simple")] + [(set_attr "neon_type" "neon_bp_simple")] ) (define_insn "neon_vget_lane_zext_internal" @@ -2696,12 +2687,11 @@ ops[0] = operands[0]; ops[1] = gen_rtx_REG (mode, regno + 2 * (elt / halfelts)); ops[2] = GEN_INT (elt_adj); - output_asm_insn ("vmov%?.u\t%0, %P1[%c2]", ops); + output_asm_insn ("vmov.u\t%0, %P1[%c2]", ops); return ""; } - [(set_attr "predicable" "yes") - (set_attr "neon_type" "neon_bp_simple")] + [(set_attr "neon_type" "neon_bp_simple")] ) (define_expand "neon_vget_lane" @@ -2832,10 +2822,9 @@ [(set (match_operand:VX 0 "s_register_operand" "=w") (vec_duplicate:VX (match_operand: 1 "s_register_operand" "r")))] "TARGET_NEON" - "vdup%?.\t%0, %1" + "vdup.\t%0, %1" ;; Assume this schedules like vmov. - [(set_attr "predicable" "yes") - (set_attr "neon_type" "neon_bp_simple")] + [(set_attr "neon_type" "neon_bp_simple")] ) (define_insn "neon_vdup_n" @@ -2843,11 +2832,10 @@ (vec_duplicate:V32 (match_operand: 1 "s_register_operand" "r,t")))] "TARGET_NEON" "@ - vdup%?.\t%0, %1 - vdup%?.\t%0, %y1" + vdup.\t%0, %1 + vdup.\t%0, %y1" ;; Assume this schedules like vmov. - [(set_attr "predicable" "yes") - (set_attr "neon_type" "neon_bp_simple")] + [(set_attr "neon_type" "neon_bp_simple")] ) (define_expand "neon_vdup_ndi" @@ -2865,10 +2853,9 @@ (vec_duplicate:V2DI (match_operand:DI 1 "s_register_operand" "r,w")))] "TARGET_NEON" "@ - vmov%?\t%e0, %Q1, %R1\;vmov%?\t%f0, %Q1, %R1 - vmov%?\t%e0, %P1\;vmov%?\t%f0, %P1" - [(set_attr "predicable" "yes") - (set_attr "length" "8") + vmov\t%e0, %Q1, %R1\;vmov\t%f0, %Q1, %R1 + vmov\t%e0, %P1\;vmov\t%f0, %P1" + [(set_attr "length" "8") (set_attr "neon_type" "neon_bp_simple")] )