From patchwork Tue Sep 6 14:15:44 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramana Radhakrishnan X-Patchwork-Id: 3889 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 9AE9423EF8 for ; Tue, 6 Sep 2011 14:16:06 +0000 (UTC) Received: from mail-fx0-f52.google.com (mail-fx0-f52.google.com [209.85.161.52]) by fiordland.canonical.com (Postfix) with ESMTP id 79161A18130 for ; Tue, 6 Sep 2011 14:16:06 +0000 (UTC) Received: by fxd18 with SMTP id 18so6330628fxd.11 for ; Tue, 06 Sep 2011 07:16:06 -0700 (PDT) Received: by 10.223.22.16 with SMTP id l16mr718760fab.62.1315318566268; Tue, 06 Sep 2011 07:16:06 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.11.8 with SMTP id m8cs99741lab; Tue, 6 Sep 2011 07:16:05 -0700 (PDT) Received: by 10.224.182.20 with SMTP id ca20mr3970312qab.84.1315318564760; Tue, 06 Sep 2011 07:16:04 -0700 (PDT) Received: from mail-iy0-f178.google.com (mail-iy0-f178.google.com [209.85.210.178]) by mx.google.com with ESMTPS id fb3si8535347qab.56.2011.09.06.07.16.04 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 06 Sep 2011 07:16:04 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.210.178 is neither permitted nor denied by best guess record for domain of ramana.radhakrishnan@linaro.org) client-ip=209.85.210.178; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.210.178 is neither permitted nor denied by best guess record for domain of ramana.radhakrishnan@linaro.org) smtp.mail=ramana.radhakrishnan@linaro.org Received: by iage36 with SMTP id e36so9560156iag.37 for ; Tue, 06 Sep 2011 07:15:44 -0700 (PDT) MIME-Version: 1.0 Received: by 10.231.61.149 with SMTP id t21mr10154188ibh.46.1315318544511; Tue, 06 Sep 2011 07:15:44 -0700 (PDT) Received: by 10.231.31.4 with HTTP; Tue, 6 Sep 2011 07:15:44 -0700 (PDT) Date: Tue, 6 Sep 2011 15:15:44 +0100 Message-ID: Subject: [PATCH ARM] Fix PR50099 From: Ramana Radhakrishnan To: gcc-patches Cc: Patch Tracking Hi, PR target/50099 is a case where we are using the wrong predicate for the sign_extend from QI to DImode values. ldrsb has a lower range than the other ldrb instructions in ARM state and hence one has to be careful about generating the right addresses when splitting it. Attached is a patch to fix this. I will commit this if there are no regressions. A backport to 4.6 branch will be done after suitable regression testing. cheers Ramana 2011-09-06 Ramana Radhakrishnan PR target/50099 * config/arm/iterators.md (qhs_zextenddi_cstr): New. (qhs_zextenddi_op): New. * config/arm/arm.md ("zero_extenddi2"): Use them. * config/arm/predicates.md ("arm_extendqisi_mem_op"): Distinguish between ARM and Thumb2 states. PR target/50099 * gcc.target/arm/pr50099.c: New test. commit 9c268f1a74578ae082ea52dfcc655804b8319190 Author: Ramana Radhakrishnan Date: Tue Sep 6 15:14:14 2011 +0100 Fix PR target/50099 diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 40341bd..388254f 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -4163,8 +4163,8 @@ (define_insn "zero_extenddi2" [(set (match_operand:DI 0 "s_register_operand" "=r") - (zero_extend:DI (match_operand:QHSI 1 "" - "")))] + (zero_extend:DI (match_operand:QHSI 1 "" + "")))] "TARGET_32BIT " "#" [(set_attr "length" "8") diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 219918c..da1f7af 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -390,10 +390,14 @@ (define_mode_attr qhs_zextenddi_cond [(SI "") (HI "&& arm_arch6") (QI "")]) (define_mode_attr qhs_sextenddi_cond [(SI "") (HI "&& arm_arch6") (QI "&& arm_arch6")]) -(define_mode_attr qhs_extenddi_op [(SI "s_register_operand") +(define_mode_attr qhs_zextenddi_op [(SI "s_register_operand") (HI "nonimmediate_operand") (QI "nonimmediate_operand")]) -(define_mode_attr qhs_extenddi_cstr [(SI "r") (HI "rm") (QI "rm")]) +(define_mode_attr qhs_extenddi_op [(SI "s_register_operand") + (HI "nonimmediate_operand") + (QI "arm_reg_or_extendqisi_mem_op")]) +(define_mode_attr qhs_extenddi_cstr [(SI "r") (HI "rm") (QI "rUq")]) +(define_mode_attr qhs_zextenddi_cstr [(SI "r") (HI "rm") (QI "rm")]) ;; Mode attributes used for fixed-point support. (define_mode_attr qaddsub_suf [(V4UQQ "8") (V2UHQ "16") (UQQ "8") (UHQ "16") diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index cfe8d33..50c1b43 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -296,8 +296,11 @@ (define_special_predicate "arm_extendqisi_mem_op" (and (match_operand 0 "memory_operand") - (match_test "arm_legitimate_address_outer_p (mode, XEXP (op, 0), - SIGN_EXTEND, 0)"))) + (match_test "TARGET_ARM ? arm_legitimate_address_outer_p (mode, + XEXP (op, 0), + SIGN_EXTEND, + 0) + : memory_address_p (QImode, XEXP (op, 0))"))) (define_special_predicate "arm_reg_or_extendqisi_mem_op" (ior (match_operand 0 "arm_extendqisi_mem_op") diff --git a/gcc/testsuite/gcc.target/arm/pr50099.c b/gcc/testsuite/gcc.target/arm/pr50099.c new file mode 100644 index 0000000..e767423 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr50099.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ + +typedef signed char int8_t ; +typedef signed short int16_t; +typedef signed long int32_t; +typedef signed long long int64_t; + +int64_t foo (int8_t * arg) +{ + int64_t temp_1; + + temp_1 = arg[256]; // index must be > 255 to ice! + return temp_1; +}