From patchwork Thu Apr 7 07:42:33 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ira Rosen X-Patchwork-Id: 928 Return-Path: Delivered-To: unknown Received: from imap.gmail.com (74.125.159.109) by localhost6.localdomain6 with IMAP4-SSL; 08 Jun 2011 14:47:26 -0000 Delivered-To: patches@linaro.org Received: by 10.68.52.132 with SMTP id t4cs51470pbo; Thu, 7 Apr 2011 00:42:35 -0700 (PDT) Received: by 10.236.190.132 with SMTP id e4mr626033yhn.374.1302162155314; Thu, 07 Apr 2011 00:42:35 -0700 (PDT) Received: from mail-gy0-f178.google.com (mail-gy0-f178.google.com [209.85.160.178]) by mx.google.com with ESMTPS id 62si2999986yhl.161.2011.04.07.00.42.33 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 07 Apr 2011 00:42:34 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.160.178 is neither permitted nor denied by best guess record for domain of ira.rosen@linaro.org) client-ip=209.85.160.178; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.160.178 is neither permitted nor denied by best guess record for domain of ira.rosen@linaro.org) smtp.mail=ira.rosen@linaro.org Received: by gyd12 with SMTP id 12so1134318gyd.37 for ; Thu, 07 Apr 2011 00:42:33 -0700 (PDT) MIME-Version: 1.0 Received: by 10.151.12.7 with SMTP id p7mr468143ybi.144.1302162153455; Thu, 07 Apr 2011 00:42:33 -0700 (PDT) Received: by 10.150.197.13 with HTTP; Thu, 7 Apr 2011 00:42:33 -0700 (PDT) Date: Thu, 7 Apr 2011 09:42:33 +0200 Message-ID: Subject: [patch, ARM] Fix PR target/48252 From: Ira Rosen To: gcc-patches@gcc.gnu.org Cc: Patch Tracking , Ulrich Weigand Hi, This patch makes both outputs of neon_vzip/vuzp/vtrn_internal explicitly dependent on both inputs, preventing incorrect optimization: for (a,b)<- vzip (c,d) and (e,f) <- vzip (g,d) CSE decides that b==f, since b and f depend only on d. Tested on arm-linux-gnueabi. OK for trunk? OK for 4.6 after testing? Thanks, Ira ChangeLog: 2011-04-07 Ulrich Weigand Ira Rosen PR target/48252 * config/arm/arm.c (neon_emit_pair_result_insn): Swap arguments to match neon_vzip/vuzp/vtrn_internal. * config/arm/neon.md (neon_vtrn_internal): Make both outputs explicitly dependent on both inputs. (neon_vzip_internal, neon_vuzp_internal): Likewise. testsuite/Changelog: PR target/48252 * gcc.target/arm/pr48252.c: New test. Index: testsuite/gcc.target/arm/pr48252.c =================================================================== --- testsuite/gcc.target/arm/pr48252.c (revision 0) +++ testsuite/gcc.target/arm/pr48252.c (revision 0) @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_neon_hw } */ +/* { dg-options "-O2" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" +#include + +int main(void) +{ + uint8x8_t v1 = {1, 1, 1, 1, 1, 1, 1, 1}; + uint8x8_t v2 = {2, 2, 2, 2, 2, 2, 2, 2}; + uint8x8x2_t vd1, vd2; + union {uint8x8_t v; uint8_t buf[8];} d1, d2, d3, d4; + int i; + + vd1 = vzip_u8(v1, vdup_n_u8(0)); + vd2 = vzip_u8(v2, vdup_n_u8(0)); + + vst1_u8(d1.buf, vd1.val[0]); + vst1_u8(d2.buf, vd1.val[1]); + vst1_u8(d3.buf, vd2.val[0]); + vst1_u8(d4.buf, vd2.val[1]); + + for (i = 0; i < 8; i++) + if ((i % 2 == 0 && d4.buf[i] != 2) + || (i % 2 == 1 && d4.buf[i] != 0)) + abort (); + + return 0; +} Index: config/arm/arm.c =================================================================== --- config/arm/arm.c (revision 172019) +++ config/arm/arm.c (working copy) @@ -19593,7 +19593,7 @@ neon_emit_pair_result_insn (enum machine rtx tmp1 = gen_reg_rtx (mode); rtx tmp2 = gen_reg_rtx (mode); - emit_insn (intfn (tmp1, op1, tmp2, op2)); + emit_insn (intfn (tmp1, op1, op2, tmp2)); emit_move_insn (mem, tmp1); mem = adjust_address (mem, mode, GET_MODE_SIZE (mode)); Index: config/arm/neon.md =================================================================== --- config/arm/neon.md (revision 172019) +++ config/arm/neon.md (working copy) @@ -4092,13 +4092,14 @@ (define_insn "neon_vtrn_internal" [(set (match_operand:VDQW 0 "s_register_operand" "=w") - (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")] - UNSPEC_VTRN1)) - (set (match_operand:VDQW 2 "s_register_operand" "=w") - (unspec:VDQW [(match_operand:VDQW 3 "s_register_operand" "2")] - UNSPEC_VTRN2))] + (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0") + (match_operand:VDQW 2 "s_register_operand" "w")] + UNSPEC_VTRN1)) + (set (match_operand:VDQW 3 "s_register_operand" "=2") + (unspec:VDQW [(match_dup 1) (match_dup 2)] + UNSPEC_VTRN2))] "TARGET_NEON" - "vtrn.\t%0, %2" + "vtrn.\t%0, %3" [(set (attr "neon_type") (if_then_else (ne (symbol_ref "") (const_int 0)) (const_string "neon_bp_simple") @@ -4118,13 +4119,14 @@ (define_insn "neon_vzip_internal" [(set (match_operand:VDQW 0 "s_register_operand" "=w") - (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")] - UNSPEC_VZIP1)) - (set (match_operand:VDQW 2 "s_register_operand" "=w") - (unspec:VDQW [(match_operand:VDQW 3 "s_register_operand" "2")] - UNSPEC_VZIP2))] + (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0") + (match_operand:VDQW 2 "s_register_operand" "w")] + UNSPEC_VZIP1)) + (set (match_operand:VDQW 3 "s_register_operand" "=2") + (unspec:VDQW [(match_dup 1) (match_dup 2)] + UNSPEC_VZIP2))] "TARGET_NEON" - "vzip.\t%0, %2" + "vzip.\t%0, %3" [(set (attr "neon_type") (if_then_else (ne (symbol_ref "") (const_int 0)) (const_string "neon_bp_simple") @@ -4144,13 +4146,14 @@ (define_insn "neon_vuzp_internal" [(set (match_operand:VDQW 0 "s_register_operand" "=w") - (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")] + (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0") + (match_operand:VDQW 2 "s_register_operand" "w")] UNSPEC_VUZP1)) - (set (match_operand:VDQW 2 "s_register_operand" "=w") - (unspec:VDQW [(match_operand:VDQW 3 "s_register_operand" "2")] - UNSPEC_VUZP2))] + (set (match_operand:VDQW 3 "s_register_operand" "=2") + (unspec:VDQW [(match_dup 1) (match_dup 2)] + UNSPEC_VUZP2))] "TARGET_NEON" - "vuzp.\t%0, %2" + "vuzp.\t%0, %3" [(set (attr "neon_type") (if_then_else (ne (symbol_ref "") (const_int 0)) (const_string "neon_bp_simple")