From patchwork Tue Oct 18 14:45:02 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernd Edlinger X-Patchwork-Id: 78066 Delivered-To: patch@linaro.org Received: by 10.140.97.247 with SMTP id m110csp921475qge; Tue, 18 Oct 2016 07:45:40 -0700 (PDT) X-Received: by 10.98.102.221 with SMTP id s90mr1352712pfj.146.1476801940240; Tue, 18 Oct 2016 07:45:40 -0700 (PDT) Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id u83si36074786pfk.205.2016.10.18.07.45.39 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Oct 2016 07:45:40 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-438930-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-438930-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-438930-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:references:in-reply-to :content-type:mime-version; q=dns; s=default; b=l0V6JGUj38D4Hzy6 5Ni1Yvo7HC3IHEizlFK9feXQZ3dHMw3lHVAeRG2BGMlwyWyinrmlqp1Shop5bGkz 45g7qJ/k4XMAiIG2nIzy0xCq8Fn09pqy7gT3ep2hYBsERxObmbu4bCUFvtvLbAZE aAB2mgXca/3/EEDtYkgCb3Ny710= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:references:in-reply-to :content-type:mime-version; s=default; bh=w6lHEp6aojKKdQWetFMLmA 3RDXM=; b=w8znVnuS+KSvvFwFf7yraBcwPxOBspC9BhFWyrjbneJPcFi4l/og2o 9CH63OqSc45cvMzNJ144R76qeX59JVHN4LyxUbJUWLTp88JkwYXgK3swXGraQKIT Jxw6sgM5ylcMdTs24aSTufoIx3GrqpXekyRjKMKvVZwYZSFsdkmSw= Received: (qmail 85938 invoked by alias); 18 Oct 2016 14:45:28 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 85891 invoked by uid 89); 18 Oct 2016 14:45:24 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 spammy=SHIFT, REG_P, reg_p, Clearing X-HELO: SNT004-OMC2S41.hotmail.com Received: from snt004-omc2s41.hotmail.com (HELO SNT004-OMC2S41.hotmail.com) (65.54.61.92) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 18 Oct 2016 14:45:14 +0000 Received: from EUR01-HE1-obe.outbound.protection.outlook.com ([65.55.90.71]) by SNT004-OMC2S41.hotmail.com over TLS secured channel with Microsoft SMTPSVC(7.5.7601.23008); Tue, 18 Oct 2016 07:45:09 -0700 Received: from HE1EUR01FT048.eop-EUR01.prod.protection.outlook.com (10.152.0.51) by HE1EUR01HT201.eop-EUR01.prod.protection.outlook.com (10.152.1.211) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.669.7; Tue, 18 Oct 2016 14:45:02 +0000 Received: from AM4PR0701MB2162.eurprd07.prod.outlook.com (10.152.0.56) by HE1EUR01FT048.mail.protection.outlook.com (10.152.1.17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.669.7 via Frontend Transport; Tue, 18 Oct 2016 14:45:02 +0000 Received: from AM4PR0701MB2162.eurprd07.prod.outlook.com ([10.167.132.147]) by AM4PR0701MB2162.eurprd07.prod.outlook.com ([10.167.132.147]) with mapi id 15.01.0679.006; Tue, 18 Oct 2016 14:45:02 +0000 From: Bernd Edlinger To: Christophe Lyon , Kyrill Tkachov CC: Eric Botcazou , Richard Biener , "gcc-patches@gcc.gnu.org" , Nick Clifton , Richard Earnshaw , Ramana Radhakrishnan Subject: Re: [PATCH] Reduce stack usage in sha512 (PR target/77308) Date: Tue, 18 Oct 2016 14:45:02 +0000 Message-ID: References: <5106795.3uCmH4qeSv@polaris> <580500A9.4060804@foss.arm.com> In-Reply-To: authentication-results: linaro.org; dkim=none (message not signed) header.d=none; linaro.org; dmarc=none action=none header.from=hotmail.de; x-ms-exchange-messagesentrepresentingtype: 1 x-eopattributedmessage: 0 x-microsoft-exchange-diagnostics: 1; HE1EUR01HT201; 6:Doon8Ng6T4fjR6flHZKk/nSMMCslb0BoNnJaSy1y7QNDwVt5UYWGpn01so5Rhx4EflVP5HTxyXzQqU9IW0IZcVgYO9dBMj4zUhISnbWUlEu2DVfpWWdCAYuYTlQqUNfmqgR9cgguttkx3R5HRBkaxnvxOwTORotg0u3OKSvlWdIaWMYiqiVF9Ug4e8WhobVPlR/uHvtpZuN2k2jDLPmow2Rt9h/KaIiog/MAyv+IkAueeixE97hNbSM3POR6BGMD395sTzA3YW6G8TEWvA91fQqcdGNFXnpcCCiSnY4WDdgYUsv7lDkSGNyA+hXxxWFn; 5:qvhY/xkfBnTUzXvTwtAtFxs8PPjNDe05g2cdPe01FxVGiXVVYId5POmw3Qbzy9zQ5KKK9ntS1F1Pti1MQyeuUKYeOyaZksITL090lrF2AWk7ZuZTRuYCClCw9QssEA0rvSLcViecJMjAU0yGwz1x6g==; 24:C5ziut25YMbUNp54bMVPsD/LkZJzRKmgTis9uPj5ZDOsNf0KtexaVglDdZuAmt2KWNSlIR7t7TVrPhrE0753Y/7PAwaHTEkL/twKf9GMh9g=; 7:Dn4TZilxt1rSP21VaGL0VAJiplMFrmdMvbaB/Zi4WmVen9zyjTwjfuXCmNbQNC0jU6FIq/BsvJd1y8CuJHaNPrygCtK9HkckQYx4KbaJRZpl+SnUDxVmA+ayFQWYfEpI790zsq5VC+//lR3Z59LAPzqzUx344/3HTBmDd3c31yuwCwEAkORkVekALB0twt2A2KnuiiWrOp547kSP+yfKwuHhkA/x6vnYBS50uWbltt7Ob+yJd7NllgCAChqxxoAlcFt9O5HKzPt0W8uzhLOmLuZ2Fr4UDAsuclPYhmTl+tprqleUHj/XNweT9nQDGMoRGYNrWwe778sOgFetB2jnq2EwUelkI9EGyWcsGWA3Ds8= x-forefront-antispam-report: EFV:NLI; SFV:NSPM; SFS:(10019020)(98900003); DIR:OUT; SFP:1102; SCL:1; SRVR:HE1EUR01HT201; H:AM4PR0701MB2162.eurprd07.prod.outlook.com; FPR:; SPF:None; LANG:en; x-ms-office365-filtering-correlation-id: c7bc917b-04eb-481c-08d7-08d3f76556fd x-microsoft-antispam: UriScan:; BCL:0; PCL:0; RULEID:(1601124038)(1603103081)(1601125047); SRVR:HE1EUR01HT201; x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(432015012)(102415321)(82015046); SRVR:HE1EUR01HT201; BCL:0; PCL:0; RULEID:; SRVR:HE1EUR01HT201; x-forefront-prvs: 00997889E7 spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: outlook.com X-MS-Exchange-CrossTenant-originalarrivaltime: 18 Oct 2016 14:45:02.4342 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Internet X-MS-Exchange-CrossTenant-id: 84df9e7f-e9f6-40af-b435-aaaaaaaaaaaa X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1EUR01HT201 On 10/18/16 10:36, Christophe Lyon wrote: > > I am seeing a lot of regressions since this patch was committed: > http://people.linaro.org/~christophe.lyon/cross-validation/gcc/trunk/241273/report-build-info.html > > (you can click on "REGRESSED" to see the list of regressions, "sum" > and "log" to download > the corresponding .sum/.log) > > Thanks, > > Christophe > Oh, sorry, I have completely missed that. Unfortunately I have tested one of the good combinations. I have not considered the case that in and out could be the same register. But that happens here. This should solve it. Can you give it a try? Thanks Bernd. 2016-10-18 Bernd Edlinger * config/arm/arm.c (arm_emit_coreregs_64bit_shift): Clear the result register only if "in" and "out" are different registers. --- gcc/config/arm/arm.c.orig 2016-10-17 11:00:34.045673223 +0200 +++ gcc/config/arm/arm.c 2016-10-18 14:53:06.710101327 +0200 @@ -29218,8 +29218,10 @@ arm_emit_coreregs_64bit_shift (enum rtx_ /* Clearing the out register in DImode first avoids lots of spilling and results in less stack usage. - Later this redundant insn is completely removed. */ - emit_insn (SET (out, const0_rtx)); + Later this redundant insn is completely removed. + Do that only if "in" and "out" are different registers. */ + if (REG_P (out) && REG_P (in) && REGNO (out) != REGNO (in)) + emit_insn (SET (out, const0_rtx)); emit_insn (SET (out_down, LSHIFT (code, in_down, amount))); emit_insn (SET (out_down, ORR (REV_LSHIFT (code, in_up, reverse_amount), @@ -29231,11 +29233,14 @@ arm_emit_coreregs_64bit_shift (enum rtx_ /* Shifts by a constant greater than 31. */ rtx adj_amount = GEN_INT (INTVAL (amount) - 32); - emit_insn (SET (out, const0_rtx)); + if (REG_P (out) && REG_P (in) && REGNO (out) != REGNO (in)) + emit_insn (SET (out, const0_rtx)); emit_insn (SET (out_down, SHIFT (code, in_up, adj_amount))); if (code == ASHIFTRT) emit_insn (gen_ashrsi3 (out_up, in_up, GEN_INT (31))); + else + emit_insn (SET (out_up, const0_rtx)); } } else