From patchwork Mon Nov 21 11:24:58 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Preudhomme X-Patchwork-Id: 83206 Delivered-To: patch@linaro.org Received: by 10.182.1.168 with SMTP id 8csp1469386obn; Mon, 21 Nov 2016 03:25:27 -0800 (PST) X-Received: by 10.55.133.134 with SMTP id h128mr14579821qkd.190.1479727527895; Mon, 21 Nov 2016 03:25:27 -0800 (PST) Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id e12si13139754qkh.332.2016.11.21.03.25.27 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 21 Nov 2016 03:25:27 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-442118-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-442118-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-442118-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :references:subject:to:from:message-id:date:mime-version :in-reply-to:content-type; q=dns; s=default; b=gBUBwgwAGhwEGgNY7 hFPgIbHrWhuR+km9nNfMSBps+piXn7IE98xXBWgtdczM5diw9I3Y6mEvDMKNgvFD +ujTxYJh0yIidDcrTUIe0cDCcxRlZD63PcOGCl0ZCpH2WTIu9F+0joQ1iFueaxwA YRAtqND3MPPABh/Uc+PNRas0LY= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :references:subject:to:from:message-id:date:mime-version :in-reply-to:content-type; s=default; bh=t/DIjUjxYFa+DAlDs/xcA3/ KuZc=; b=T3ev3iCeZk1Tt5J5DR+C86UX/x+dRliTYSfNbYK5ZLSvj+dXQTvVENH ydibskrB8Hgn+Em+y7fqaP+r/sPmkQaMV4AnQSM1ZAETZey6QltWCFC8fi25F7y9 3SRx3++kLNEANs7sTbzdY83FL0nXq3mOf+bhErM3JfnC4W90G8N4= Received: (qmail 23158 invoked by alias); 21 Nov 2016 11:25:14 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 23138 invoked by uid 89); 21 Nov 2016 11:25:12 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.9 required=5.0 tests=BAYES_00, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=rk, sk:embedde, l0, sk:const_i X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 21 Nov 2016 11:25:02 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1D0CA28; Mon, 21 Nov 2016 03:25:00 -0800 (PST) Received: from [10.2.206.52] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C36423F220 for ; Mon, 21 Nov 2016 03:24:59 -0800 (PST) References: <0ce9ef69-cf59-075e-d392-f5bed829c4d8@foss.arm.com> Subject: [arm-embedded][PATCH, GCC/ARM] Fix ICE when compiling empty FIQ interrupt handler in ARM mode To: "gcc-patches@gcc.gnu.org" From: Thomas Preudhomme X-Forwarded-Message-Id: <0ce9ef69-cf59-075e-d392-f5bed829c4d8@foss.arm.com> Message-ID: <94949f71-152c-75ad-1250-1d1ed0a4e976@foss.arm.com> Date: Mon, 21 Nov 2016 11:24:58 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.3.0 MIME-Version: 1.0 In-Reply-To: <0ce9ef69-cf59-075e-d392-f5bed829c4d8@foss.arm.com> X-IsSubscribed: yes Hi, We have decided to backport this patch to fix an internal compiler error when compiling an empty FIX interrupt handler to our embedded-6-branch. *** gcc/ChangeLog.arm *** 2016-11-17 Thomas Preud'homme Backport from mainline 2016-11-16 Thomas Preud'homme * config/arm/arm.md (arm_addsi3): Add alternative for addition of general register with general register or ARM constant into SP register. *** gcc/testsuite/ChangeLog.arm *** 2016-11-17 Thomas Preud'homme Backport from mainline 2016-11-16 Thomas Preud'homme * gcc.target/arm/empty_fiq_handler.c: New test. Hi, This patch fixes the following ICE when building when compiling an empty FIQ interrupt handler in ARM mode: empty_fiq_handler.c:5:1: error: insn does not satisfy its constraints: } ^ (insn/f 13 12 14 (set (reg/f:SI 13 sp) (plus:SI (reg/f:SI 11 fp) (const_int 4 [0x4]))) irq.c:5 4 {*arm_addsi3} (expr_list:REG_CFA_ADJUST_CFA (set (reg/f:SI 13 sp) (plus:SI (reg/f:SI 11 fp) (const_int 4 [0x4]))) (nil))) The ICE was provoked by missing an alternative to reflect that ARM mode can do an add of general register into sp which is unpredictable in Thumb mode add immediate. ChangeLog entries are as follow: *** gcc/ChangeLog *** 2016-11-04 Thomas Preud'homme * config/arm/arm.md (arm_addsi3): Add alternative for addition of general register with general register or ARM constant into SP register. *** gcc/testsuite/ChangeLog *** 2016-11-04 Thomas Preud'homme * gcc.target/arm/empty_fiq_handler.c: New test. Testing: bootstrapped on ARMv7-A ARM mode & testsuite shows no regression. Is this ok for trunk? Best regards, Thomas diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 8393f65bcf4c9c3e61b91e5adcd5f59ff7c6ec3f..70cd31f6cb176fe29efc1fbbf692bfc270ef5a1b 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -609,9 +609,9 @@ ;; (plus (reg rN) (reg sp)) into (reg rN). In this case reload will ;; put the duplicated register first, and not try the commutative version. (define_insn_and_split "*arm_addsi3" - [(set (match_operand:SI 0 "s_register_operand" "=rk,l,l ,l ,r ,k ,r,r ,k ,r ,k,k,r ,k ,r") - (plus:SI (match_operand:SI 1 "s_register_operand" "%0 ,l,0 ,l ,rk,k ,r,rk,k ,rk,k,r,rk,k ,rk") - (match_operand:SI 2 "reg_or_int_operand" "rk ,l,Py,Pd,rI,rI,k,Pj,Pj,L ,L,L,PJ,PJ,?n")))] + [(set (match_operand:SI 0 "s_register_operand" "=rk,l,l ,l ,r ,k ,r,k ,r ,k ,r ,k,k,r ,k ,r") + (plus:SI (match_operand:SI 1 "s_register_operand" "%0 ,l,0 ,l ,rk,k ,r,r ,rk,k ,rk,k,r,rk,k ,rk") + (match_operand:SI 2 "reg_or_int_operand" "rk ,l,Py,Pd,rI,rI,k,rI,Pj,Pj,L ,L,L,PJ,PJ,?n")))] "TARGET_32BIT" "@ add%?\\t%0, %0, %2 @@ -621,6 +621,7 @@ add%?\\t%0, %1, %2 add%?\\t%0, %1, %2 add%?\\t%0, %2, %1 + add%?\\t%0, %1, %2 addw%?\\t%0, %1, %2 addw%?\\t%0, %1, %2 sub%?\\t%0, %1, #%n2 @@ -640,10 +641,10 @@ operands[1], 0); DONE; " - [(set_attr "length" "2,4,4,4,4,4,4,4,4,4,4,4,4,4,16") + [(set_attr "length" "2,4,4,4,4,4,4,4,4,4,4,4,4,4,4,16") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no,no,no,no,no,no,no") - (set_attr "arch" "t2,t2,t2,t2,*,*,*,t2,t2,*,*,a,t2,t2,*") + (set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no,no,no,no,no,no,no,no") + (set_attr "arch" "t2,t2,t2,t2,*,*,*,a,t2,t2,*,*,a,t2,t2,*") (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") (const_string "alu_imm") (const_string "alu_sreg"))) diff --git a/gcc/testsuite/gcc.target/arm/empty_fiq_handler.c b/gcc/testsuite/gcc.target/arm/empty_fiq_handler.c new file mode 100644 index 0000000000000000000000000000000000000000..bbcfd0e32f9d0cc60c8a013fd1bb584b21aaad16 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/empty_fiq_handler.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ + +/* Below code used to trigger an ICE due to missing constraints for + sp = fp + cst pattern. */ + +void fiq_handler (void) __attribute__((interrupt ("FIQ"))); + +void +fiq_handler (void) +{ +}