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[209.132.180.131]) by mx.google.com with ESMTPS id e5si65504123pgd.7.2017.01.04.07.44.49 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 04 Jan 2017 07:44:49 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-445373-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-445373-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-445373-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:from:message-id:date:mime-version :in-reply-to:content-type; q=dns; s=default; b=hRTQpSsQvD09CwzRQ Mb5r8ZOlktT/LUZD9qk3euLJCceKIpGaLqGdopD/aZmfAnnQ+xOHUW361E5V113f Kr4HnJ4w5l1TbZdJvqPTI+l5RmBqA6tDPLdeN9kc8LfChPF+opgJaHOGBVPytEl4 iM/MeUIR4IaiQT+qwMn+9C0oXc= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:from:message-id:date:mime-version :in-reply-to:content-type; s=default; bh=/nIAWLSAoDw8vqyXJHbgEM4 nfHg=; b=BqwDeRoOKNZ+ro/fUIe3M3M3Zd6Hf9P4gs6aZ6q2HenqUVbBZvL0o5w IP09Vxj2iUGKHuHQy8VJ6AHn9Kw34z3ELtDrcMXZ9d54YRDq7mHSTTMqr2PqdgwR bLbq3gzaKHEgvWOE7m2fYk0UNrKhuhFm1OsNuZmMzN+0Vqqk6sbo= Received: (qmail 72179 invoked by alias); 4 Jan 2017 15:44:35 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 72155 invoked by uid 89); 4 Jan 2017 15:44:35 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-4.1 required=5.0 tests=BAYES_00, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=H*f:sk:586CC39, H*i:sk:586CC39, H*MI:sk:586CC39, H*M:219d X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 04 Jan 2017 15:44:25 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 324E5154D; Wed, 4 Jan 2017 07:44:23 -0800 (PST) Received: from [10.2.206.52] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 733E33F24D; Wed, 4 Jan 2017 07:44:22 -0800 (PST) Subject: Re: [PATCH, GCC/testsuite/ARM, ping] Fix empty_fiq_handler target selector To: Kyrill Tkachov , Ramana Radhakrishnan , Richard Earnshaw , "gcc-patches@gcc.gnu.org" References: <477e3617-d4d3-1381-fb17-9b205dd7e670@foss.arm.com> <586CC393.1050407@foss.arm.com> From: Thomas Preudhomme Message-ID: <90542165-4a24-3a5a-219d-7d00ccbc71e8@foss.arm.com> Date: Wed, 4 Jan 2017 15:44:21 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.5.1 MIME-Version: 1.0 In-Reply-To: <586CC393.1050407@foss.arm.com> X-IsSubscribed: yes On 04/01/17 09:42, Kyrill Tkachov wrote: > > On 03/01/17 17:22, Thomas Preudhomme wrote: >> Happy new year! >> >> Ping? >> >> Best regards, >> >> Thomas >> >> On 09/12/16 15:28, Thomas Preudhomme wrote: >>> Hi, >>> >>> The current target selector for empty_fiq_handler.c testcase skips the test when >>> targeting Thumb mode on a device with ARM execution state. Because it checks >>> Thumb mode by looking for an -mthumb option it fails to work when GCC was >>> configured with --with-mode=thumb. It is also too restrictive because interrupt >>> handler can be compiled in Thumb-2. This patch checks the arm_thumb1 effective >>> target instead of the -mthumb flag to fix both issues. >>> >>> ChangeLog entry is as follows: >>> >>> >>> *** gcc/testsuite/ChangeLog *** >>> >>> 2016-12-09 Thomas Preud'homme >>> >>> * gcc.target/arm/empty_fiq_handler: Skip instead if targeting Thumb-1 >>> on a non Thumb-only target. >>> >>> >>> Tested with GCC built for ARMv5T and ARMv7-A with --with-mode=thumb and >>> --with-mode=arm and for ARMv6S-M with --with-mode=thumb: >>> >>> * test pass in all cases for ARMv5T and ARMv7-A with -marm >>> * test pass in all cases for ARMv6S-M and ARMv7-A with -mthumb >>> * test pass without option when defaulting to ARM for ARMv5T and ARMv7-A >>> * test pass without option when defaulting to Thumb for ARMv6S-M and ARMv7-A >>> * test is unsupported with -marm for ARMv5T >>> * test is unsupported without option when defaulting to Thumb for ARMv5T >>> >>> Is this ok for stage3? >>> >>> Best regards, >>> >>> Thomas >> >> fix_empty_fiq_handler_testcase_selector.patch >> >> >> diff --git a/gcc/testsuite/gcc.target/arm/empty_fiq_handler.c >> b/gcc/testsuite/gcc.target/arm/empty_fiq_handler.c >> index >> 8313f2199122be153a737946e817a5e3bee60372..69bb0669dd416e1fcb015c278d62961d071fc42f >> 100644 >> --- a/gcc/testsuite/gcc.target/arm/empty_fiq_handler.c >> +++ b/gcc/testsuite/gcc.target/arm/empty_fiq_handler.c >> @@ -1,5 +1,4 @@ >> -/* { dg-do compile } */ >> -/* { dg-skip-if "" { ! arm_cortex_m } { "-mthumb" } } */ >> +/* { dg-do compile { target { {! arm_thumb1 } || arm_cortex_m } } } */ >> > > I think you want to add a space between the '{' and '!'. > Otherwise this is ok. Right. Did testing with ARMv4T defaulting to Thumb and ARMv7-A defaulting to Thumb and ARM to make sure it didn't seem to affect the behavior. Committed as r244057 with suggested change (attached for reference). Best regards, Thomas diff --git a/gcc/testsuite/gcc.target/arm/empty_fiq_handler.c b/gcc/testsuite/gcc.target/arm/empty_fiq_handler.c index 8313f2199122be153a737946e817a5e3bee60372..7b8296bfc903780d35059e2e63ed7ef35daf51d1 100644 --- a/gcc/testsuite/gcc.target/arm/empty_fiq_handler.c +++ b/gcc/testsuite/gcc.target/arm/empty_fiq_handler.c @@ -1,5 +1,4 @@ -/* { dg-do compile } */ -/* { dg-skip-if "" { ! arm_cortex_m } { "-mthumb" } } */ +/* { dg-do compile { target { { ! arm_thumb1 } || arm_cortex_m } } } */ /* Below code used to trigger an ICE due to missing constraints for sp = fp + cst pattern. */