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[209.132.180.131]) by mx.google.com with ESMTPS id v10si7630417plg.543.2017.12.09.15.13.24 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 09 Dec 2017 15:13:24 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-468854-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=aw9g3jHA; spf=pass (google.com: domain of gcc-patches-return-468854-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-468854-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:references:date:in-reply-to:message-id:mime-version :content-type; q=dns; s=default; b=nIGvkirG0CShgRFvthsJF/DibvgYE YJMOuKXVQbJVzUa9aVTsUylB3G6qeVXxusvkj4Xbo6d/GJ94yq93XPeo7Uoy5kt2 sh4kafdB/TNJ/lAhLS+JNX5nBGFYDCsXe/TZxmykwqj9LbN9+eXT7VEb4Rfz6tae TwzC52m3NtArh4= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:references:date:in-reply-to:message-id:mime-version :content-type; s=default; bh=UfmczKpUBozUvGAuia96igDtMAQ=; b=aw9 g3jHATlvB2/n5NQTwKUEhac8KixJxy98Z2v360Oeq8Ug5rhus25/GxvmlK+frbD1 n7EjpsU5FoQAHzd8Qhc2tuRWseoOxOW5JqA3zGt36c3Gpxd4ZMZJcmQPR8kEGD6i ciOEoU0SI940iq7Job9HaF+/sxyIbFPuu0m11t+M= Received: (qmail 91131 invoked by alias); 9 Dec 2017 23:13:11 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 91119 invoked by uid 89); 9 Dec 2017 23:13:10 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-11.0 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=Broadcast X-HELO: mail-wr0-f176.google.com Received: from mail-wr0-f176.google.com (HELO mail-wr0-f176.google.com) (209.85.128.176) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sat, 09 Dec 2017 23:13:08 +0000 Received: by mail-wr0-f176.google.com with SMTP id g53so14027037wra.2 for ; Sat, 09 Dec 2017 15:13:07 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:mail-followup-to:subject:references:date :in-reply-to:message-id:user-agent:mime-version; bh=Y2EwoA1UgyXIgegAbAAdG7qpI1muj35HJTnKzONUrb8=; b=B4nzUXxZzykXs1yvDYQwWit9SLWPF6/7MncSc9ZyyhofoSW5u8Tw+xOJo8HQcxOzbj +7VYmhPzSa7fAlXJ6WemiNPEA4psI9mO+QIErTD8G26I5nicFFPZcbo5Y4dZWrlRgckV zf8nGRbzUTSdYKazeIzkkdNQnA8jeQXOjQdacO/hJlmuYkHGcctKY+gwLKxJHkmK1bUI AIr3PzYOgQ25SvJT+b/aBQtMUmH1bPdUsedEZSU23Wu92VR0zVCCpmAueuphbSjPXAPM ha5PUi5zbUjyzBu9Olk3gTYENNO/3EYgtyz4jdSwdt8/AYydCzMNPlj+vpvudiN0m1k5 4+ng== X-Gm-Message-State: AJaThX78xLbygKJXAzqcymDB/4U5GNlZe0E6w0X7ZiztJ0I26HpLormM frfxqSofTlrwfYie+HTUDMyFEpQ2hpA= X-Received: by 10.223.166.51 with SMTP id k48mr29726071wrc.125.1512861185389; Sat, 09 Dec 2017 15:13:05 -0800 (PST) Received: from localhost ([2.25.234.120]) by smtp.gmail.com with ESMTPSA id i65sm5742065wme.20.2017.12.09.15.13.03 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 09 Dec 2017 15:13:04 -0800 (PST) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@linaro.org Subject: [04/13] Refactor expand_vec_perm References: <87indfmrgt.fsf@linaro.org> Date: Sat, 09 Dec 2017 23:13:03 +0000 In-Reply-To: <87indfmrgt.fsf@linaro.org> (Richard Sandiford's message of "Sat, 09 Dec 2017 23:06:26 +0000") Message-ID: <87zi6rlclc.fsf@linaro.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.3 (gnu/linux) MIME-Version: 1.0 This patch splits the variable handling out of expand_vec_perm into a subroutine, so that the next patch can use a different interface for expanding constant permutes. expand_vec_perm now does all the CONST_VECTOR handling directly and defers to expand_vec_perm_var for other rtx codes. Handling CONST_VECTORs includes handling the fallback to variable permutes. The patch also adds an assert for valid optab modes to expand_vec_perm_1, so that we get it when using optabs for CONST_VECTORs. The MODE_VECTOR_INT part was previously in expand_vec_perm and the mode_for_int_vector part is new. Most of the patch is just reindentation, so I've attached a -b version. 2017-12-06 Richard Sandiford gcc/ * optabs.c (expand_vec_perm_1): Assert that SEL has an integer vector mode and that that mode matches the mode of the data being permuted. (expand_vec_perm): Split handling of non-CONST_VECTOR selectors out into expand_vec_perm_var. Do all CONST_VECTOR handling here, directly using expand_vec_perm_1 when forcing selectors into registers. (expand_vec_perm_var): New function, split out from expand_vec_perm. Index: gcc/optabs.c =================================================================== --- gcc/optabs.c 2017-12-09 23:06:57.167722990 +0000 +++ gcc/optabs.c 2017-12-09 23:11:09.452859833 +0000 @@ -5405,6 +5405,8 @@ expand_vec_perm_1 (enum insn_code icode, machine_mode smode = GET_MODE (sel); struct expand_operand ops[4]; + gcc_assert (GET_MODE_CLASS (smode) == MODE_VECTOR_INT + || mode_for_int_vector (tmode).require () == smode); create_output_operand (&ops[0], target, tmode); create_input_operand (&ops[3], sel, smode); @@ -5431,8 +5433,13 @@ expand_vec_perm_1 (enum insn_code icode, return NULL_RTX; } -/* Generate instructions for vec_perm optab given its mode - and three operands. */ +static rtx expand_vec_perm_var (machine_mode, rtx, rtx, rtx, rtx); + +/* Implement a permutation of vectors v0 and v1 using the permutation + vector in SEL and return the result. Use TARGET to hold the result + if nonnull and convenient. + + MODE is the mode of the vectors being permuted (V0 and V1). */ rtx expand_vec_perm (machine_mode mode, rtx v0, rtx v1, rtx sel, rtx target) @@ -5443,6 +5450,9 @@ expand_vec_perm (machine_mode mode, rtx rtx tmp, sel_qi = NULL; rtvec vec; + if (GET_CODE (sel) != CONST_VECTOR) + return expand_vec_perm_var (mode, v0, v1, sel, target); + if (!target || GET_MODE (target) != mode) target = gen_reg_rtx (mode); @@ -5455,22 +5465,18 @@ expand_vec_perm (machine_mode mode, rtx if (!qimode_for_vec_perm (mode).exists (&qimode)) qimode = VOIDmode; - /* If the input is a constant, expand it specially. */ - gcc_assert (GET_MODE_CLASS (GET_MODE (sel)) == MODE_VECTOR_INT); - if (GET_CODE (sel) == CONST_VECTOR) - { /* See if this can be handled with a vec_shr. We only do this if the second vector is all zeroes. */ - enum insn_code shift_code = optab_handler (vec_shr_optab, mode); - enum insn_code shift_code_qi = ((qimode != VOIDmode && qimode != mode) + insn_code shift_code = optab_handler (vec_shr_optab, mode); + insn_code shift_code_qi = ((qimode != VOIDmode && qimode != mode) ? optab_handler (vec_shr_optab, qimode) : CODE_FOR_nothing); - rtx shift_amt = NULL_RTX; + if (v1 == CONST0_RTX (GET_MODE (v1)) && (shift_code != CODE_FOR_nothing || shift_code_qi != CODE_FOR_nothing)) { - shift_amt = shift_amt_for_vec_perm_mask (sel); + rtx shift_amt = shift_amt_for_vec_perm_mask (sel); if (shift_amt) { struct expand_operand ops[3]; @@ -5478,19 +5484,16 @@ expand_vec_perm (machine_mode mode, rtx { create_output_operand (&ops[0], target, mode); create_input_operand (&ops[1], v0, mode); - create_convert_operand_from_type (&ops[2], shift_amt, - sizetype); + create_convert_operand_from_type (&ops[2], shift_amt, sizetype); if (maybe_expand_insn (shift_code, 3, ops)) return ops[0].value; } if (shift_code_qi != CODE_FOR_nothing) { - tmp = gen_reg_rtx (qimode); + rtx tmp = gen_reg_rtx (qimode); create_output_operand (&ops[0], tmp, qimode); - create_input_operand (&ops[1], gen_lowpart (qimode, v0), - qimode); - create_convert_operand_from_type (&ops[2], shift_amt, - sizetype); + create_input_operand (&ops[1], gen_lowpart (qimode, v0), qimode); + create_convert_operand_from_type (&ops[2], shift_amt, sizetype); if (maybe_expand_insn (shift_code_qi, 3, ops)) return gen_lowpart (mode, ops[0].value); } @@ -5525,16 +5528,62 @@ expand_vec_perm (machine_mode mode, rtx icode = direct_optab_handler (vec_perm_const_optab, qimode); if (icode != CODE_FOR_nothing) { - tmp = mode != qimode ? gen_reg_rtx (qimode) : target; + tmp = gen_reg_rtx (qimode); tmp = expand_vec_perm_1 (icode, tmp, gen_lowpart (qimode, v0), gen_lowpart (qimode, v1), sel_qi); if (tmp) return gen_lowpart (mode, tmp); } } - } /* Otherwise expand as a fully variable permuation. */ + + icode = direct_optab_handler (vec_perm_optab, mode); + if (icode != CODE_FOR_nothing) + { + rtx tmp = expand_vec_perm_1 (icode, target, v0, v1, sel); + if (tmp) + return tmp; + } + + if (qimode != VOIDmode) + { + icode = direct_optab_handler (vec_perm_optab, qimode); + if (icode != CODE_FOR_nothing) + { + rtx tmp = gen_reg_rtx (qimode); + tmp = expand_vec_perm_1 (icode, tmp, gen_lowpart (qimode, v0), + gen_lowpart (qimode, v1), sel_qi); + if (tmp) + return gen_lowpart (mode, tmp); + } + } + + return NULL_RTX; +} + +/* Implement a permutation of vectors v0 and v1 using the permutation + vector in SEL and return the result. Use TARGET to hold the result + if nonnull and convenient. + + MODE is the mode of the vectors being permuted (V0 and V1). + SEL must have the integer equivalent of MODE and is known to be + unsuitable for permutes with a constant permutation vector. */ + +static rtx +expand_vec_perm_var (machine_mode mode, rtx v0, rtx v1, rtx sel, rtx target) +{ + enum insn_code icode; + unsigned int i, w, u; + rtx tmp, sel_qi; + rtvec vec; + + w = GET_MODE_SIZE (mode); + u = GET_MODE_UNIT_SIZE (mode); + + if (!target || GET_MODE (target) != mode) + target = gen_reg_rtx (mode); + icode = direct_optab_handler (vec_perm_optab, mode); if (icode != CODE_FOR_nothing) { @@ -5545,22 +5594,20 @@ expand_vec_perm (machine_mode mode, rtx /* As a special case to aid several targets, lower the element-based permutation to a byte-based permutation and try again. */ - if (qimode == VOIDmode) + machine_mode qimode; + if (!qimode_for_vec_perm (mode).exists (&qimode)) return NULL_RTX; icode = direct_optab_handler (vec_perm_optab, qimode); if (icode == CODE_FOR_nothing) return NULL_RTX; - if (sel_qi == NULL) - { /* Multiply each element by its byte size. */ machine_mode selmode = GET_MODE (sel); if (u == 2) sel = expand_simple_binop (selmode, PLUS, sel, sel, NULL, 0, OPTAB_DIRECT); else - sel = expand_simple_binop (selmode, ASHIFT, sel, - GEN_INT (exact_log2 (u)), + sel = expand_simple_binop (selmode, ASHIFT, sel, GEN_INT (exact_log2 (u)), NULL, 0, OPTAB_DIRECT); gcc_assert (sel != NULL); @@ -5588,7 +5635,6 @@ expand_vec_perm (machine_mode mode, rtx sel_qi = expand_simple_binop (qimode, PLUS, sel, tmp, sel, 0, OPTAB_DIRECT); gcc_assert (sel_qi != NULL); - } tmp = mode != qimode ? gen_reg_rtx (qimode) : target; tmp = expand_vec_perm_1 (icode, tmp, gen_lowpart (qimode, v0),