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[209.132.180.131]) by mx.google.com with ESMTPS id n69si6399924pfk.349.2017.09.11.10.16.27 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 Sep 2017 10:16:28 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-461839-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=k6u2aU9w; spf=pass (google.com: domain of gcc-patches-return-461839-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-461839-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; q=dns; s= default; b=Z2w2H7qCCTSIg6xNHAbwR42/dhpFmlGRwtkAk8J2yub2tlfPfJbRk 9nqHFqri2xBPm/xycV9ofdr2QJfKRRWkC3lrzTotb9VsJi2cLRBzsEhx/1eRCYfo DaomBv52hzc7QyhvHIlEGQ6bkbpwfx58lhKQ5IWWgghSvhlRLck3bU= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; s= default; bh=bwVGPH6Mh4+2rDsvgzDJvkb9ss4=; b=k6u2aU9w7dpgpsqlMCqK OWmvXQFIzO5l25mq5MDITFOUQUVbN9Ht4by8B17f9vn12XVKdOk6YCsIftBrbF3k Gq7zSwvZ9U1wvW7DiLo2NtwWWiL/CH6WMk7t0fA/GcX1wn4S2AeWtq5f2K5hLfJ3 x8UCOOONLV8BFTjcBb0ENbk= Received: (qmail 45772 invoked by alias); 11 Sep 2017 17:16:15 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 45557 invoked by uid 89); 11 Sep 2017 17:16:15 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-15.6 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-wm0-f51.google.com Received: from mail-wm0-f51.google.com (HELO mail-wm0-f51.google.com) (74.125.82.51) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 11 Sep 2017 17:16:13 +0000 Received: by mail-wm0-f51.google.com with SMTP id f199so44992450wme.0 for ; Mon, 11 Sep 2017 10:16:13 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:mail-followup-to:subject:date:message-id :user-agent:mime-version; bh=Uw6cfsSSldJOOToFKeA6um2bZ6h1onNx0R33nQ5migQ=; b=U6/VjjcLsOw9BFjA2qweX/y0suKkiEkXSP5jM2CMuyDwTxzhf8dktNsSZF4ruQO9/w T+jxQ/TpKgex5gDwl7e0Yi5N4cfbd7Ru5jGML4zmzjY8J3s40hstdgQyrKmUhdX2kRKh GYHFzn4V996whYSgoHxuz0VA7brTYfGnX8SAXWRAVcBQ7CsLWO7AgkNX6g6+0VjEx4rI b1l0bFj77mracroitfEPLhx9EPf+ojw/mLVk5sW5SGg1YRNaLUTzI/ROrBIbq922dvUF s3v8imL6QwbJpHE06P1BCpMSA8ciGzIMHqL7O7R8ggm+oU5v4/7MrQbJfYkLMhelvNiC bIQg== X-Gm-Message-State: AHPjjUhnQHAZ+y0Le2lCJX+O61CmEzqCKQeQPc/zZk0+nhe/u4A3eSa4 jbVegSpFs2VqWC3aZ4I2X0jLWkphkPo= X-Google-Smtp-Source: AOwi7QAvmzx7QEPVTSKt+yj8zyZjv9vtppYIDSZa6p/6+ejjm5OvFv5ffkx3Z0FaC52lx8JSRkAu/g== X-Received: by 10.28.91.73 with SMTP id p70mr9805093wmb.13.1505150171176; Mon, 11 Sep 2017 10:16:11 -0700 (PDT) Received: from localhost ([2.25.234.0]) by smtp.gmail.com with ESMTPSA id f19sm17164367wrf.85.2017.09.11.10.16.10 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 11 Sep 2017 10:16:10 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@linaro.org Subject: Make more use of end_hard_regno Date: Mon, 11 Sep 2017 18:16:09 +0100 Message-ID: <87r2vdcg12.fsf@linaro.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.2 (gnu/linux) MIME-Version: 1.0 An upcoming patch will convert hard_regno_nregs into an inline function, which in turn allows hard_regno_nregs to be used as the name of a targetm field. This patch rewrites uses that can use end_hard_regno instead. Tested on aarch64-linux-gnu, x86_64-linux-gnu and powerpc64le-linux-gnu. Also tested by comparing the testsuite assembly output on at least one target per CPU directory. OK to install? Richard 2017-09-11 Richard Sandiford gcc/ * config/aarch64/aarch64.c (aarch64_hard_regno_mode_ok): Use end_hard_regno instead of hard_regno_nregs. * config/s390/s390.c (s390_reg_clobbered_rtx): Likewise. * config/sparc/sparc.h (ASM_DECLARE_REGISTER_GLOBAL): Likewise. * config/visium/visium.c (visium_hard_regno_mode_ok): Likewise. * ira-color.c (improve_allocation): Likewise. * lra-assigns.c (find_hard_regno_for_1): Likewise. * lra-lives.c (mark_regno_live): Likewise. (mark_regno_dead): Likewise. * lra-remat.c (operand_to_remat): Likewise. * lra.c (collect_non_operand_hard_regs): Likewise. * postreload.c (reload_combine_note_store): Likewise. (move2add_valid_value_p): Likewise. * reload.c (regno_clobbered_p): Likewise. Index: gcc/config/aarch64/aarch64.c =================================================================== --- gcc/config/aarch64/aarch64.c 2017-09-11 17:20:21.469287471 +0100 +++ gcc/config/aarch64/aarch64.c 2017-09-11 17:20:21.705282714 +0100 @@ -1106,8 +1106,7 @@ aarch64_hard_regno_mode_ok (unsigned reg if (FP_REGNUM_P (regno)) { if (aarch64_vect_struct_mode_p (mode)) - return - (regno + aarch64_hard_regno_nregs (regno, mode) - 1) <= V31_REGNUM; + return end_hard_regno (mode, regno) - 1 <= V31_REGNUM; else return true; } Index: gcc/config/s390/s390.c =================================================================== --- gcc/config/s390/s390.c 2017-09-11 17:20:21.469287471 +0100 +++ gcc/config/s390/s390.c 2017-09-11 17:20:21.706282694 +0100 @@ -9630,7 +9630,7 @@ s390_reg_clobbered_rtx (rtx setreg, cons return; for (i = regno; - i < regno + HARD_REGNO_NREGS (regno, mode); + i < end_hard_regno (mode, regno); i++) regs_ever_clobbered[i] = 1; } Index: gcc/config/sparc/sparc.h =================================================================== --- gcc/config/sparc/sparc.h 2017-09-11 17:20:21.469287471 +0100 +++ gcc/config/sparc/sparc.h 2017-09-11 17:20:21.707282674 +0100 @@ -1248,7 +1248,7 @@ #define ASM_DECLARE_REGISTER_GLOBAL(FILE do { \ if (TARGET_ARCH64) \ { \ - int end = HARD_REGNO_NREGS ((REGNO), DECL_MODE (decl)) + (REGNO); \ + int end = end_hard_regno (DECL_MODE (decl), REGNO); \ int reg; \ for (reg = (REGNO); reg < 8 && reg < end; reg++) \ if ((reg & ~1) == 2 || (reg & ~1) == 6) \ Index: gcc/config/visium/visium.c =================================================================== --- gcc/config/visium/visium.c 2017-09-11 17:20:21.469287471 +0100 +++ gcc/config/visium/visium.c 2017-09-11 17:20:21.707282674 +0100 @@ -857,7 +857,7 @@ visium_hard_regno_rename_ok (unsigned in visium_hard_regno_mode_ok (unsigned int regno, machine_mode mode) { if (GP_REGISTER_P (regno)) - return GP_REGISTER_P (regno + HARD_REGNO_NREGS (regno, mode) - 1); + return GP_REGISTER_P (end_hard_regno (mode, regno) - 1); if (FP_REGISTER_P (regno)) return mode == SFmode || (mode == SImode && TARGET_FPU_IEEE); Index: gcc/ira-color.c =================================================================== --- gcc/ira-color.c 2017-09-11 17:20:21.469287471 +0100 +++ gcc/ira-color.c 2017-09-11 17:20:21.708282653 +0100 @@ -2893,7 +2893,7 @@ improve_allocation (void) conflict_nregs = hard_regno_nregs[conflict_hregno][ALLOCNO_MODE (conflict_a)]; for (r = conflict_hregno; - r >= 0 && r + hard_regno_nregs[r][mode] > conflict_hregno; + r >= 0 && (int) end_hard_regno (mode, r) > conflict_hregno; r--) if (check_hard_reg_p (a, r, conflicting_regs, profitable_hard_regs)) Index: gcc/lra-assigns.c =================================================================== --- gcc/lra-assigns.c 2017-09-11 17:20:21.469287471 +0100 +++ gcc/lra-assigns.c 2017-09-11 17:20:21.708282653 +0100 @@ -578,7 +578,7 @@ find_hard_regno_for_1 (int regno, int *c hr++) SET_HARD_REG_BIT (impossible_start_hard_regs, hr); for (hr = conflict_hr - 1; - hr >= 0 && hr + hard_regno_nregs[hr][biggest_mode] > conflict_hr; + hr >= 0 && (int) end_hard_regno (biggest_mode, hr) > conflict_hr; hr--) SET_HARD_REG_BIT (impossible_start_hard_regs, hr); } Index: gcc/lra-lives.c =================================================================== --- gcc/lra-lives.c 2017-09-11 17:20:21.469287471 +0100 +++ gcc/lra-lives.c 2017-09-11 17:20:21.708282653 +0100 @@ -314,9 +314,7 @@ mark_regno_live (int regno, machine_mode if (regno < FIRST_PSEUDO_REGISTER) { - for (last = regno + hard_regno_nregs[regno][mode]; - regno < last; - regno++) + for (last = end_hard_regno (mode, regno); regno < last; regno++) make_hard_regno_born (regno, false); } else @@ -343,9 +341,7 @@ mark_regno_dead (int regno, machine_mode if (regno < FIRST_PSEUDO_REGISTER) { - for (last = regno + hard_regno_nregs[regno][mode]; - regno < last; - regno++) + for (last = end_hard_regno (mode, regno); regno < last; regno++) make_hard_regno_dead (regno); } else Index: gcc/lra-remat.c =================================================================== --- gcc/lra-remat.c 2017-09-11 17:20:21.469287471 +0100 +++ gcc/lra-remat.c 2017-09-11 17:20:21.708282653 +0100 @@ -367,8 +367,7 @@ operand_to_remat (rtx_insn *insn) if (reg2->type == OP_OUT && reg->regno <= reg2->regno && (reg2->regno - < (reg->regno - + hard_regno_nregs[reg->regno][reg->biggest_mode]))) + < (int) end_hard_regno (reg->biggest_mode, reg->regno))) return -1; } /* Check hard coded insn registers. */ Index: gcc/lra.c =================================================================== --- gcc/lra.c 2017-09-11 17:20:21.469287471 +0100 +++ gcc/lra.c 2017-09-11 17:20:21.709282633 +0100 @@ -843,9 +843,7 @@ collect_non_operand_hard_regs (rtx *x, l return list; /* Process all regs even unallocatable ones as we need info about all regs for rematerialization pass. */ - for (last = regno + hard_regno_nregs[regno][mode]; - regno < last; - regno++) + for (last = end_hard_regno (mode, regno); regno < last; regno++) { for (curr = list; curr != NULL; curr = curr->next) if (curr->regno == regno && curr->subreg_p == subreg_p Index: gcc/postreload.c =================================================================== --- gcc/postreload.c 2017-09-11 17:20:21.469287471 +0100 +++ gcc/postreload.c 2017-09-11 17:20:21.709282633 +0100 @@ -1453,7 +1453,7 @@ reload_combine_note_store (rtx dst, cons if (GET_CODE (SET_DEST (set)) == ZERO_EXTRACT || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART) { - for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--) + for (i = end_hard_regno (mode, regno) - 1; i >= regno; i--) { reg_state[i].use_index = -1; reg_state[i].store_ruid = reload_combine_ruid; @@ -1462,7 +1462,7 @@ reload_combine_note_store (rtx dst, cons } else { - for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--) + for (i = end_hard_regno (mode, regno) - 1; i >= regno; i--) { reg_state[i].store_ruid = reload_combine_ruid; if (GET_CODE (set) == SET) @@ -1717,8 +1717,8 @@ move2add_valid_value_p (int regno, scala return false; } - for (int i = hard_regno_nregs[regno][mode] - 1; i > 0; i--) - if (reg_mode[regno + i] != BLKmode) + for (int i = end_hard_regno (mode, regno) - 1; i > regno; i--) + if (reg_mode[i] != BLKmode) return false; return true; } Index: gcc/reload.c =================================================================== --- gcc/reload.c 2017-09-11 17:20:21.469287471 +0100 +++ gcc/reload.c 2017-09-11 17:20:21.710282613 +0100 @@ -7180,13 +7180,10 @@ reg_inc_found_and_valid_p (unsigned int regno_clobbered_p (unsigned int regno, rtx_insn *insn, machine_mode mode, int sets) { - unsigned int nregs, endregno; - /* regno must be a hard register. */ gcc_assert (regno < FIRST_PSEUDO_REGISTER); - nregs = hard_regno_nregs[regno][mode]; - endregno = regno + nregs; + unsigned int endregno = end_hard_regno (mode, regno); if ((GET_CODE (PATTERN (insn)) == CLOBBER || (sets == 1 && GET_CODE (PATTERN (insn)) == SET))