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[209.132.180.131]) by mx.google.com with ESMTPS id j10si684375pfe.285.2017.08.22.02.21.08 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 22 Aug 2017 02:21:08 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-460690-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=yP8ktnkI; spf=pass (google.com: domain of gcc-patches-return-460690-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-460690-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; q=dns; s= default; b=twOMQr2tZAmXS+3HL5AnriYiyJCns8LhCMA0WD7ubKMBEvreuW0Hx bGmJYeGn0d8+JQMKItTyvcg/KYw9ZjKi3k/ME6EMd/Ly6dMvurAQshoLwm1QVBPZ jAhhTxrQvAQRH7hoSj14+RP5HqQbd0ggiuMTarTMjtB3ELHTjWpRCc= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; s= default; bh=E4R2PPcOFsRkLnlLyAPatH1X7Xo=; b=yP8ktnkIt5V68SACY0dl 4tcWSZGingGIrdrBlkyEUnYABbbcaFZf/ml4dnQ+fXsLNQA3h9UoDdas+Xseekdx bZLvao7HCkbotpUx1Kydu5RvRapb+3rGmm4nZWoJm8B3AsB8Aj2zQduUlfV1Pd4X E27j5xthVna6jg01HXj0Yr8= Received: (qmail 106002 invoked by alias); 22 Aug 2017 09:20:54 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 105988 invoked by uid 89); 22 Aug 2017 09:20:53 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-10.3 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM, SPF_PASS autolearn=ham version=3.3.2 spammy=Quad X-HELO: mail-wr0-f174.google.com Received: from mail-wr0-f174.google.com (HELO mail-wr0-f174.google.com) (209.85.128.174) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 22 Aug 2017 09:20:51 +0000 Received: by mail-wr0-f174.google.com with SMTP id p14so51146133wrg.1 for ; Tue, 22 Aug 2017 02:20:50 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:mail-followup-to:subject:date:message-id :user-agent:mime-version; bh=CvUEFKqxMRHS9DDzkxCpc4UE/bQI/QAw2+NugB96CuE=; b=lgsL69xQ3WzpCzvnhAxtO7xecxJcaiWTgWbT5eQprHFlwMXvroN0AsBfznDQKe8wvl 1VkAjaYs8tvTAVq7jI9mwO/hD4Xk8PlDuYMW5qDQ+FCONvV7Z0U1phOV0jOKnGjEeRhb L7lgmNT9taamroBv9mkcrJByBsvkoybxrleEP9EBvX2ol8QJ42PbWHUkoFKI5X+xmjwb cTacqh+c09teQ3/ayrC113k0K6e1fGmP4angGgXBJMP3HIaJf1JegC/M11rmtLkxVzN7 tuyNBOzL6gExB2IB8L5eA685RAiSllOIrRU0v+LChm0rqdXVp+bzBbrZT2c6fHqpTfH1 RJwA== X-Gm-Message-State: AHYfb5hhMkUt3Z4UQCTlQBODUpB0ClYRJZtfUIPaw1jeOFgBBaloMvrW M72l5nekcxzwCnuNQG721w== X-Received: by 10.28.14.20 with SMTP id 20mr10102wmo.124.1503393648293; Tue, 22 Aug 2017 02:20:48 -0700 (PDT) Received: from localhost ([95.145.139.63]) by smtp.gmail.com with ESMTPSA id t135sm12711182wmt.23.2017.08.22.02.20.47 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 22 Aug 2017 02:20:47 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@linaro.org Subject: [AArch64] Remove use of wider vector modes Date: Tue, 22 Aug 2017 10:20:46 +0100 Message-ID: <87efs4c61d.fsf@linaro.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/25.2 (gnu/linux) MIME-Version: 1.0 The AArch64 port defined x2, x3 and x4 vector modes that were only used in the rtl for the AdvSIMD LD{2,3,4} patterns. It seems unlikely that this rtl would have led to any valid simplifications, since the values involved were unspecs that had a different number of operands from the non-dreg versions. (The dreg UNSPEC_LD2 had a single operand, while the qreg one had two operands.) As it happened, the patterns led to invalid simplifications on big- endian targets due to a mix-up in the operand order, see Tamar's fix in r240271. This patch therefore replaces the rtl patterns with dedicated unspecs. This allows the x2, x3 and x4 modes to be removed, avoiding a clash with 256-bit and 512-bit SVE. Tested on aarch64-linux-gnu. Also tested by comparing the before and after assembly for the testsuite at -O2 -ftree-vectorize on aarch64-linux-gnu and aarch64_be-linux-gnu; there were no differences. OK to install? Richard 2017-08-22 Richard Sandiford Alan Hayward David Sherwood gcc/ * config/aarch64/aarch64-modes.def: Remove 32-, 48- and 64-byte vector modes. * config/aarch64/iterators.md (VRL2, VRL3, VRL4): Delete. * config/aarch64/aarch64.md (UNSPEC_LD2_DREG, UNSPEC_LD3_DREG) (UNSPEC_LD4_DREG): New unspecs. * config/aarch64/aarch64-simd.md (aarch64_ld2_dreg_le) (aarch64_ld2_dreg_be): Replace with... (aarch64_ld2_dreg): ...this pattern and use the new DREG unspec. (aarch64_ld3_dreg_le) (aarch64_ld3_dreg_be): Replace with... (aarch64_ld3_dreg): ...this pattern and use the new DREG unspec. (aarch64_ld4_dreg_le) (aarch64_ld4_dreg_be): Replace with... (aarch64_ld4_dreg): ...this pattern and use the new DREG unspec. Index: gcc/config/aarch64/aarch64-modes.def =================================================================== --- gcc/config/aarch64/aarch64-modes.def 2017-02-23 19:54:24.000000000 +0000 +++ gcc/config/aarch64/aarch64-modes.def 2017-08-22 10:11:04.724056356 +0100 @@ -44,15 +44,5 @@ INT_MODE (OI, 32); INT_MODE (CI, 48); INT_MODE (XI, 64); -/* Vector modes for register lists. */ -VECTOR_MODES (INT, 32); /* V32QI V16HI V8SI V4DI. */ -VECTOR_MODES (FLOAT, 32); /* V8SF V4DF. */ - -VECTOR_MODES (INT, 48); /* V32QI V16HI V8SI V4DI. */ -VECTOR_MODES (FLOAT, 48); /* V8SF V4DF. */ - -VECTOR_MODES (INT, 64); /* V32QI V16HI V8SI V4DI. */ -VECTOR_MODES (FLOAT, 64); /* V8SF V4DF. */ - /* Quad float: 128-bit floating mode for long doubles. */ FLOAT_MODE (TF, 16, ieee_quad_format); Index: gcc/config/aarch64/iterators.md =================================================================== --- gcc/config/aarch64/iterators.md 2017-08-03 10:40:55.896279339 +0100 +++ gcc/config/aarch64/iterators.md 2017-08-22 10:11:04.727125997 +0100 @@ -711,21 +711,6 @@ (define_mode_attr Vendreg [(OI "T") (CI ;; ld..._lane and st..._lane operations. (define_mode_attr nregs [(OI "2") (CI "3") (XI "4")]) -(define_mode_attr VRL2 [(V8QI "V32QI") (V4HI "V16HI") - (V4HF "V16HF") - (V2SI "V8SI") (V2SF "V8SF") - (DI "V4DI") (DF "V4DF")]) - -(define_mode_attr VRL3 [(V8QI "V48QI") (V4HI "V24HI") - (V4HF "V24HF") - (V2SI "V12SI") (V2SF "V12SF") - (DI "V6DI") (DF "V6DF")]) - -(define_mode_attr VRL4 [(V8QI "V64QI") (V4HI "V32HI") - (V4HF "V32HF") - (V2SI "V16SI") (V2SF "V16SF") - (DI "V8DI") (DF "V8DF")]) - ;; Mode for atomic operation suffixes (define_mode_attr atomic_sfx [(QI "b") (HI "h") (SI "") (DI "")]) Index: gcc/config/aarch64/aarch64.md =================================================================== --- gcc/config/aarch64/aarch64.md 2017-08-16 08:50:34.060622654 +0100 +++ gcc/config/aarch64/aarch64.md 2017-08-22 10:11:04.726102783 +0100 @@ -98,10 +98,13 @@ (define_c_enum "unspec" [ UNSPEC_GOTTINYTLS UNSPEC_LD1 UNSPEC_LD2 + UNSPEC_LD2_DREG UNSPEC_LD2_DUP UNSPEC_LD3 + UNSPEC_LD3_DREG UNSPEC_LD3_DUP UNSPEC_LD4 + UNSPEC_LD4_DREG UNSPEC_LD4_DUP UNSPEC_LD2_LANE UNSPEC_LD3_LANE Index: gcc/config/aarch64/aarch64-simd.md =================================================================== --- gcc/config/aarch64/aarch64-simd.md 2017-08-17 17:29:27.227162205 +0100 +++ gcc/config/aarch64/aarch64-simd.md 2017-08-22 10:11:04.726102783 +0100 @@ -4963,278 +4963,62 @@ (define_expand "aarch64_ld_dreg_le" +(define_insn "aarch64_ld2_dreg" [(set (match_operand:OI 0 "register_operand" "=w") - (subreg:OI - (vec_concat: - (vec_concat: - (unspec:VD - [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")] - UNSPEC_LD2) - (vec_duplicate:VD (const_int 0))) - (vec_concat: - (unspec:VD [(match_dup 1)] - UNSPEC_LD2) - (vec_duplicate:VD (const_int 0)))) 0))] - "TARGET_SIMD && !BYTES_BIG_ENDIAN" - "ld2\\t{%S0. - %T0.}, %1" - [(set_attr "type" "neon_load2_2reg")] -) - -(define_insn "aarch64_ld2_dreg_be" - [(set (match_operand:OI 0 "register_operand" "=w") - (subreg:OI - (vec_concat: - (vec_concat: - (vec_duplicate:VD (const_int 0)) - (unspec:VD - [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")] - UNSPEC_LD2)) - (vec_concat: - (vec_duplicate:VD (const_int 0)) - (unspec:VD [(match_dup 1)] - UNSPEC_LD2))) 0))] - "TARGET_SIMD && BYTES_BIG_ENDIAN" + (unspec:OI [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv") + (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_LD2_DREG))] + "TARGET_SIMD" "ld2\\t{%S0. - %T0.}, %1" [(set_attr "type" "neon_load2_2reg")] ) -(define_insn "aarch64_ld2_dreg_le" - [(set (match_operand:OI 0 "register_operand" "=w") - (subreg:OI - (vec_concat: - (vec_concat: - (unspec:DX - [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")] - UNSPEC_LD2) - (const_int 0)) - (vec_concat: - (unspec:DX [(match_dup 1)] - UNSPEC_LD2) - (const_int 0))) 0))] - "TARGET_SIMD && !BYTES_BIG_ENDIAN" - "ld1\\t{%S0.1d - %T0.1d}, %1" - [(set_attr "type" "neon_load1_2reg")] -) - -(define_insn "aarch64_ld2_dreg_be" +(define_insn "aarch64_ld2_dreg" [(set (match_operand:OI 0 "register_operand" "=w") - (subreg:OI - (vec_concat: - (vec_concat: - (const_int 0) - (unspec:DX - [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")] - UNSPEC_LD2)) - (vec_concat: - (const_int 0) - (unspec:DX [(match_dup 1)] - UNSPEC_LD2))) 0))] - "TARGET_SIMD && BYTES_BIG_ENDIAN" + (unspec:OI [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv") + (unspec:DX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_LD2_DREG))] + "TARGET_SIMD" "ld1\\t{%S0.1d - %T0.1d}, %1" [(set_attr "type" "neon_load1_2reg")] ) -(define_insn "aarch64_ld3_dreg_le" +(define_insn "aarch64_ld3_dreg" [(set (match_operand:CI 0 "register_operand" "=w") - (subreg:CI - (vec_concat: - (vec_concat: - (vec_concat: - (unspec:VD - [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")] - UNSPEC_LD3) - (vec_duplicate:VD (const_int 0))) - (vec_concat: - (unspec:VD [(match_dup 1)] - UNSPEC_LD3) - (vec_duplicate:VD (const_int 0)))) - (vec_concat: - (unspec:VD [(match_dup 1)] - UNSPEC_LD3) - (vec_duplicate:VD (const_int 0)))) 0))] - "TARGET_SIMD && !BYTES_BIG_ENDIAN" - "ld3\\t{%S0. - %U0.}, %1" - [(set_attr "type" "neon_load3_3reg")] -) - -(define_insn "aarch64_ld3_dreg_be" - [(set (match_operand:CI 0 "register_operand" "=w") - (subreg:CI - (vec_concat: - (vec_concat: - (vec_concat: - (vec_duplicate:VD (const_int 0)) - (unspec:VD - [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")] - UNSPEC_LD3)) - (vec_concat: - (vec_duplicate:VD (const_int 0)) - (unspec:VD [(match_dup 1)] - UNSPEC_LD3))) - (vec_concat: - (vec_duplicate:VD (const_int 0)) - (unspec:VD [(match_dup 1)] - UNSPEC_LD3))) 0))] - "TARGET_SIMD && BYTES_BIG_ENDIAN" + (unspec:CI [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv") + (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_LD3_DREG))] + "TARGET_SIMD" "ld3\\t{%S0. - %U0.}, %1" [(set_attr "type" "neon_load3_3reg")] ) -(define_insn "aarch64_ld3_dreg_le" +(define_insn "aarch64_ld3_dreg" [(set (match_operand:CI 0 "register_operand" "=w") - (subreg:CI - (vec_concat: - (vec_concat: - (vec_concat: - (unspec:DX - [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")] - UNSPEC_LD3) - (const_int 0)) - (vec_concat: - (unspec:DX [(match_dup 1)] - UNSPEC_LD3) - (const_int 0))) - (vec_concat: - (unspec:DX [(match_dup 1)] - UNSPEC_LD3) - (const_int 0))) 0))] - "TARGET_SIMD && !BYTES_BIG_ENDIAN" - "ld1\\t{%S0.1d - %U0.1d}, %1" - [(set_attr "type" "neon_load1_3reg")] -) - -(define_insn "aarch64_ld3_dreg_be" - [(set (match_operand:CI 0 "register_operand" "=w") - (subreg:CI - (vec_concat: - (vec_concat: - (vec_concat: - (const_int 0) - (unspec:DX - [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")] - UNSPEC_LD3)) - (vec_concat: - (const_int 0) - (unspec:DX [(match_dup 1)] - UNSPEC_LD3))) - (vec_concat: - (const_int 0) - (unspec:DX [(match_dup 1)] - UNSPEC_LD3))) 0))] - "TARGET_SIMD && BYTES_BIG_ENDIAN" + (unspec:CI [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv") + (unspec:DX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_LD3_DREG))] + "TARGET_SIMD" "ld1\\t{%S0.1d - %U0.1d}, %1" [(set_attr "type" "neon_load1_3reg")] ) -(define_insn "aarch64_ld4_dreg_le" - [(set (match_operand:XI 0 "register_operand" "=w") - (subreg:XI - (vec_concat: - (vec_concat: - (vec_concat: - (unspec:VD - [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")] - UNSPEC_LD4) - (vec_duplicate:VD (const_int 0))) - (vec_concat: - (unspec:VD [(match_dup 1)] - UNSPEC_LD4) - (vec_duplicate:VD (const_int 0)))) - (vec_concat: - (vec_concat: - (unspec:VD [(match_dup 1)] - UNSPEC_LD4) - (vec_duplicate:VD (const_int 0))) - (vec_concat: - (unspec:VD [(match_dup 1)] - UNSPEC_LD4) - (vec_duplicate:VD (const_int 0))))) 0))] - "TARGET_SIMD && !BYTES_BIG_ENDIAN" - "ld4\\t{%S0. - %V0.}, %1" - [(set_attr "type" "neon_load4_4reg")] -) - -(define_insn "aarch64_ld4_dreg_be" +(define_insn "aarch64_ld4_dreg" [(set (match_operand:XI 0 "register_operand" "=w") - (subreg:XI - (vec_concat: - (vec_concat: - (vec_concat: - (vec_duplicate:VD (const_int 0)) - (unspec:VD - [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")] - UNSPEC_LD4)) - (vec_concat: - (vec_duplicate:VD (const_int 0)) - (unspec:VD [(match_dup 1)] - UNSPEC_LD4))) - (vec_concat: - (vec_concat: - (vec_duplicate:VD (const_int 0)) - (unspec:VD [(match_dup 1)] - UNSPEC_LD4)) - (vec_concat: - (vec_duplicate:VD (const_int 0)) - (unspec:VD [(match_dup 1)] - UNSPEC_LD4)))) 0))] - "TARGET_SIMD && BYTES_BIG_ENDIAN" + (unspec:XI [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv") + (unspec:VD [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_LD4_DREG))] + "TARGET_SIMD" "ld4\\t{%S0. - %V0.}, %1" [(set_attr "type" "neon_load4_4reg")] ) -(define_insn "aarch64_ld4_dreg_le" +(define_insn "aarch64_ld4_dreg" [(set (match_operand:XI 0 "register_operand" "=w") - (subreg:XI - (vec_concat: - (vec_concat: - (vec_concat: - (unspec:DX - [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")] - UNSPEC_LD4) - (const_int 0)) - (vec_concat: - (unspec:DX [(match_dup 1)] - UNSPEC_LD4) - (const_int 0))) - (vec_concat: - (vec_concat: - (unspec:DX [(match_dup 1)] - UNSPEC_LD4) - (const_int 0)) - (vec_concat: - (unspec:DX [(match_dup 1)] - UNSPEC_LD4) - (const_int 0)))) 0))] - "TARGET_SIMD && !BYTES_BIG_ENDIAN" - "ld1\\t{%S0.1d - %V0.1d}, %1" - [(set_attr "type" "neon_load1_4reg")] -) - -(define_insn "aarch64_ld4_dreg_be" - [(set (match_operand:XI 0 "register_operand" "=w") - (subreg:XI - (vec_concat: - (vec_concat: - (vec_concat: - (const_int 0) - (unspec:DX - [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")] - UNSPEC_LD4)) - (vec_concat: - (const_int 0) - (unspec:DX [(match_dup 1)] - UNSPEC_LD4))) - (vec_concat: - (vec_concat: - (const_int 0) - (unspec:DX [(match_dup 1)] - UNSPEC_LD4)) - (vec_concat: - (const_int 0) - (unspec:DX [(match_dup 1)] - UNSPEC_LD4)))) 0))] - "TARGET_SIMD && BYTES_BIG_ENDIAN" + (unspec:XI [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv") + (unspec:DX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_LD4_DREG))] + "TARGET_SIMD" "ld1\\t{%S0.1d - %V0.1d}, %1" [(set_attr "type" "neon_load1_4reg")] ) @@ -5248,12 +5032,7 @@ (define_expand "aarch64_ld * 8); - if (BYTES_BIG_ENDIAN) - emit_insn (gen_aarch64_ld_dreg_be (operands[0], - mem)); - else - emit_insn (gen_aarch64_ld_dreg_le (operands[0], - mem)); + emit_insn (gen_aarch64_ld_dreg (operands[0], mem)); DONE; })