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[209.132.180.131]) by mx.google.com with ESMTPS id j2si17441308pff.230.2019.06.26.02.35.26 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 02:35:27 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-503778-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=vsk0jzq9; dkim=neutral (body hash did not verify) header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=aURmBZI2; spf=pass (google.com: domain of gcc-patches-return-503778-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-503778-patch=linaro.org@gcc.gnu.org" DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:references:in-reply-to :content-type:mime-version; q=dns; s=default; b=kGZuxaOVTgbaAZT/ k5UOxcG/lQtPdCQyQV+1fThE+HHEnZUkIfCiDf8yvM+7KLM2UkuKbOI/vNmx2sQE 5HGoDOuQDkc3ALtpkUpu4UK/SmeLHMjrG/0FogEbkcCDbsZdILTdxbKnU2ZRciQ8 0g+3iShNWqX+HPCJ3VvDY8NFoIw= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:references:in-reply-to :content-type:mime-version; s=default; bh=EIfzC6Q0+Bw2XenLwgsjfI cVv74=; b=vsk0jzq90u+HrvmUmtCH9XMh/x0ul3CpRKEdlSe3ZHCd84wDDOyOkm Hzs/orC7TfwcBD6MK0yWsQAp5WaIWetnB9HLVqe1eUrAaC9SxEegkcPj8EreXZwG uT57afRqvtoCFNsepx6O7cbXxobSv0AUqsOClmSxHT+Rei7GWb/aQ= Received: (qmail 112538 invoked by alias); 26 Jun 2019 09:35:15 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 112530 invoked by uid 89); 26 Jun 2019 09:35:15 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-24.3 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_LOTSOFHASH, RCVD_IN_DNSWL_NONE, SPF_HELO_PASS, SPF_PASS autolearn=ham version=3.3.1 spammy=1140, Equal X-HELO: EUR02-HE1-obe.outbound.protection.outlook.com Received: from mail-eopbgr10062.outbound.protection.outlook.com (HELO EUR02-HE1-obe.outbound.protection.outlook.com) (40.107.1.62) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 26 Jun 2019 09:35:04 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ICfgW955bVdo3NpiVLhYuRM0Vlfy3nG2/yJK+04JVFE=; b=aURmBZI202KKGOZ4k6XynVWJCCuypB+mVOTwvhHEaGwLFu11evIgZEUqtHZrcuLONMGzn1CtNAlgzj2DCfw6NnaiVXMtJH1+cBYgJqCG7Xhr97ZO3Mny4scX4HEcb3H/5I0iXoqVyAS1sEy74xj9rOh8f4USmvZXceqleuwGrkY= Received: from DB6PR0801MB2054.eurprd08.prod.outlook.com (10.168.86.135) by DB6PR0801MB2085.eurprd08.prod.outlook.com (10.168.87.136) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2008.16; Wed, 26 Jun 2019 09:35:00 +0000 Received: from DB6PR0801MB2054.eurprd08.prod.outlook.com ([fe80::4114:24e6:ff51:65bb]) by DB6PR0801MB2054.eurprd08.prod.outlook.com ([fe80::4114:24e6:ff51:65bb%4]) with mapi id 15.20.2008.014; Wed, 26 Jun 2019 09:35:00 +0000 From: Joel Hutton To: GCC Patches CC: Richard Sandiford , Wilco Dijkstra , Richard Earnshaw , nd Subject: [PING][AArch64] Use scvtf fbits option where appropriate Date: Wed, 26 Jun 2019 09:35:00 +0000 Message-ID: <832dd1bd-89f9-ca98-7b88-d5b26f515d63@arm.com> References: <3157239f-48e6-bbd6-122c-d173b361bebd@arm.com> In-Reply-To: user-agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 authentication-results: spf=none (sender IP is ) smtp.mailfrom=Joel.Hutton@arm.com; x-ms-oob-tlc-oobclassifiers: OLM:1002; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 MIME-Version: 1.0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Joel.Hutton@arm.com X-IsSubscribed: yes Ping, plus minor rework (mostly non-functional changes) gcc/ChangeLog: 2019-06-12 Joel Hutton * config/aarch64/aarch64-protos.h (aarch64_fpconst_pow2_recip): New prototype * config/aarch64/aarch64.c (aarch64_fpconst_pow2_recip): New function * config/aarch64/aarch64.md (*aarch64_cvtf2_mult): New pattern (*aarch64_cvtf2_mult): New pattern * config/aarch64/constraints.md (Dt): New constraint * config/aarch64/predicates.md (aarch64_fpconst_pow2_recip): New predicate gcc/testsuite/ChangeLog: 2019-06-12 Joel Hutton * gcc.target/aarch64/fmul_scvtf_1.c: New test. Bootstrapped and regression tested on aarch64-linux-none target. >From e866ce55c9febd92ab8e6314bf79b067085b2d1b Mon Sep 17 00:00:00 2001 From: Joel Hutton Date: Wed, 19 Jun 2019 17:24:38 +0100 Subject: [PATCH] SCVTF --- gcc/config/aarch64/aarch64-protos.h | 1 + gcc/config/aarch64/aarch64.c | 23 +++ gcc/config/aarch64/aarch64.md | 39 +++++ gcc/config/aarch64/constraints.md | 7 + gcc/config/aarch64/predicates.md | 4 + .../gcc.target/aarch64/fmul_scvtf_1.c | 140 ++++++++++++++++++ 6 files changed, 214 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/fmul_scvtf_1.c diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index 1e3b1c91db1026a44f32b144a6e97398c0659feb..ad1ba458a3fa081d83acf806776e911aa789b5d0 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -494,6 +494,7 @@ enum aarch64_symbol_type aarch64_classify_tls_symbol (rtx); enum reg_class aarch64_regno_regclass (unsigned); int aarch64_asm_preferred_eh_data_format (int, int); int aarch64_fpconst_pow_of_2 (rtx); +int aarch64_fpconst_pow2_recip (rtx); machine_mode aarch64_hard_regno_caller_save_mode (unsigned, unsigned, machine_mode); int aarch64_uxt_size (int, HOST_WIDE_INT); diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 9a035dd9ed8665274249581f8c404d18ae72e873..d88716576850eedd1070de108da152838c127c36 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -18707,6 +18707,29 @@ aarch64_fpconst_pow_of_2 (rtx x) return exact_log2 (real_to_integer (r)); } +/* If X is a positive CONST_DOUBLE with a value that is the reciprocal of a + power of 2 (i.e 1/2^n) return the number of float bits. e.g. for x==(1/2^n) + return n. Otherwise return -1. */ + +int +aarch64_fpconst_pow2_recip (rtx x) +{ + REAL_VALUE_TYPE r0; + + if (!CONST_DOUBLE_P (x)) + return -1; + + r0 = *CONST_DOUBLE_REAL_VALUE (x); + if (exact_real_inverse (DFmode, &r0) + && !REAL_VALUE_NEGATIVE (r0)) + { + int ret = exact_log2 (real_to_integer (&r0)); + if (ret >= 1 && ret <= 32) + return ret; + } + return -1; +} + /* If X is a vector of equal CONST_DOUBLE values and that value is Y, return the aarch64_fpconst_pow_of_2 of Y. Otherwise return -1. */ diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 526c7fb0dabc540065d77d4a7922aeca16a402aa..0ccd5de3d807f079614b0076ac439c1cb8e56ab8 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -6016,6 +6016,44 @@ [(set_attr "type" "f_cvtf2i")] ) +;; Equal width integer to fp and multiply combine. +(define_insn "*aarch64_cvtf2_mult" + [(set (match_operand:GPF 0 "register_operand" "=w,w") + (mult:GPF (FLOATUORS:GPF + (match_operand: 1 "register_operand" "w,?r")) + (match_operand:GPF 2 "aarch64_fp_pow2_recip" "Dt,Dt")))] + "TARGET_FLOAT" + { + operands[2] = GEN_INT (aarch64_fpconst_pow2_recip (operands[2])); + switch (which_alternative) + { + case 0: + return "cvtf\t%0, %1, #%2"; + case 1: + return "cvtf\t%0, %1, #%2"; + default: + gcc_unreachable (); + } + } + [(set_attr "type" "neon_int_to_fp_,f_cvti2f") + (set_attr "arch" "simd,fp")] +) + +;; Unequal width integer to fp and multiply combine. +(define_insn "*aarch64_cvtf2_mult" + [(set (match_operand:GPF 0 "register_operand" "=w") + (mult:GPF (FLOATUORS:GPF + (match_operand: 1 "register_operand" "r")) + (match_operand:GPF 2 "aarch64_fp_pow2_recip" "Dt")))] + "TARGET_FLOAT" + { + operands[2] = GEN_INT (aarch64_fpconst_pow2_recip (operands[2])); + return "cvtf\t%0, %1, #%2"; + } + [(set_attr "type" "f_cvti2f")] +) + +;; Equal width integer to fp conversion. (define_insn "2" [(set (match_operand:GPF 0 "register_operand" "=w,w") (FLOATUORS:GPF (match_operand: 1 "register_operand" "w,?r")))] @@ -6027,6 +6065,7 @@ (set_attr "arch" "simd,fp")] ) +;; Unequal width integer to fp conversions. (define_insn "2" [(set (match_operand:GPF 0 "register_operand" "=w") (FLOATUORS:GPF (match_operand: 1 "register_operand" "r")))] diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md index 21f9549e660868900256157ea2f7154164ddd607..b0caa13b4358e89281cd5c0a75f459ceee2040f1 100644 --- a/gcc/config/aarch64/constraints.md +++ b/gcc/config/aarch64/constraints.md @@ -329,6 +329,13 @@ (match_test "aarch64_simd_scalar_immediate_valid_for_move (op, QImode)"))) +(define_constraint "Dt" + "@internal + A const_double which is the reciprocal of an exact power of two, can be + used in an scvtf with fract bits operation" + (and (match_code "const_double") + (match_test "aarch64_fpconst_pow2_recip (op) > 0"))) + (define_constraint "Dl" "@internal A constraint that matches vector of immediates for left shifts." diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md index 10100ca830a0cd753ef5759e3ce09914b1046d26..da295981286fb782c153037a7ee94203500e6f2a 100644 --- a/gcc/config/aarch64/predicates.md +++ b/gcc/config/aarch64/predicates.md @@ -98,6 +98,10 @@ (and (match_code "const_double") (match_test "aarch64_fpconst_pow_of_2 (op) > 0"))) +(define_predicate "aarch64_fp_pow2_recip" + (and (match_code "const_double") + (match_test "aarch64_fpconst_pow2_recip (op) > 0"))) + (define_predicate "aarch64_fp_vec_pow2" (match_test "aarch64_vec_fpconst_pow_of_2 (op) > 0")) diff --git a/gcc/testsuite/gcc.target/aarch64/fmul_scvtf_1.c b/gcc/testsuite/gcc.target/aarch64/fmul_scvtf_1.c new file mode 100644 index 0000000000000000000000000000000000000000..c4f271083dda212b3e78953356656ea97fe583db --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fmul_scvtf_1.c @@ -0,0 +1,140 @@ +/* { dg-do run } */ +/* { dg-options "-save-temps -O2 -fno-inline" } */ + +#define FUNC_DEFS(__a) \ +float \ +fsfoo##__a (int x) \ +{ \ + return ((float) x)/(1lu << __a); \ +} \ +float \ +fusfoo##__a (unsigned int x) \ +{ \ + return ((float) x)/(1lu << __a); \ +} \ +float \ +fslfoo##__a (long x) \ +{ \ + return ((float) x)/(1lu << __a); \ +} \ +float \ +fulfoo##__a (unsigned long x) \ +{ \ + return ((float) x)/(1lu << __a); \ +} \ + +#define FUNC_DEFD(__a) \ +double \ +dsfoo##__a (int x) \ +{ \ + return ((double) x)/(1lu << __a); \ +} \ +double \ +dusfoo##__a (unsigned int x) \ +{ \ + return ((double) x)/(1lu << __a); \ +} \ +double \ +dslfoo##__a (long x) \ +{ \ + return ((double) x)/(1lu << __a); \ +} \ +double \ +dulfoo##__a (unsigned long x) \ +{ \ + return ((double) x)/(1lu << __a); \ +} + +FUNC_DEFS (4) + /* { dg-final { scan-assembler-times "scvtf\ts\[0-9\], w\[0-9\]*.*#4" 1 } } */ + /* { dg-final { scan-assembler-times "ucvtf\ts\[0-9\], w\[0-9\]*.*#4" 1 } } */ + /* { dg-final { scan-assembler-times "scvtf\ts\[0-9\], x\[0-9\]*.*#4" 1 } } */ + /* { dg-final { scan-assembler-times "ucvtf\ts\[0-9\], x\[0-9\]*.*#4" 1 } } */ + +FUNC_DEFD (4) + /* { dg-final { scan-assembler-times "scvtf\td\[0-9\], w\[0-9\]*.*#4" 1 } } */ + /* { dg-final { scan-assembler-times "ucvtf\td\[0-9\], w\[0-9\]*.*#4" 1 } } */ + /* { dg-final { scan-assembler-times "scvtf\td\[0-9\], x\[0-9\]*.*#4" 1 } } */ + /* { dg-final { scan-assembler-times "ucvtf\td\[0-9\], x\[0-9\]*.*#4" 1 } } */ + +FUNC_DEFS (8) + /* { dg-final { scan-assembler-times "scvtf\ts\[0-9\], w\[0-9\]*.*#8" 1 } } */ + /* { dg-final { scan-assembler-times "ucvtf\ts\[0-9\], w\[0-9\]*.*#8" 1 } } */ + /* { dg-final { scan-assembler-times "scvtf\ts\[0-9\], x\[0-9\]*.*#8" 1 } } */ + /* { dg-final { scan-assembler-times "ucvtf\ts\[0-9\], x\[0-9\]*.*#8" 1 } } */ + +FUNC_DEFD (8) + /* { dg-final { scan-assembler-times "scvtf\td\[0-9\], w\[0-9\]*.*#8" 1 } } */ + /* { dg-final { scan-assembler-times "ucvtf\td\[0-9\], w\[0-9\]*.*#8" 1 } } */ + /* { dg-final { scan-assembler-times "scvtf\td\[0-9\], x\[0-9\]*.*#8" 1 } } */ + /* { dg-final { scan-assembler-times "ucvtf\td\[0-9\], x\[0-9\]*.*#8" 1 } } */ + +FUNC_DEFS (16) + /* { dg-final { scan-assembler-times "scvtf\ts\[0-9\], w\[0-9\]*.*#16" 1 } } */ + /* { dg-final { scan-assembler-times "ucvtf\ts\[0-9\], w\[0-9\]*.*#16" 1 } } */ + /* { dg-final { scan-assembler-times "scvtf\ts\[0-9\], x\[0-9\]*.*#16" 1 } } */ + /* { dg-final { scan-assembler-times "ucvtf\ts\[0-9\], x\[0-9\]*.*#16" 1 } } */ + +FUNC_DEFD (16) + /* { dg-final { scan-assembler-times "scvtf\td\[0-9\], w\[0-9\]*.*#16" 1 } } */ + /* { dg-final { scan-assembler-times "ucvtf\td\[0-9\], w\[0-9\]*.*#16" 1 } } */ + /* { dg-final { scan-assembler-times "scvtf\td\[0-9\], x\[0-9\]*.*#16" 1 } } */ + /* { dg-final { scan-assembler-times "ucvtf\td\[0-9\], x\[0-9\]*.*#16" 1 } } */ + +FUNC_DEFS (32) + /* { dg-final { scan-assembler-times "scvtf\ts\[0-9\], w\[0-9\]*.*#32" 1 } } */ + /* { dg-final { scan-assembler-times "ucvtf\ts\[0-9\], w\[0-9\]*.*#32" 1 } } */ + /* { dg-final { scan-assembler-times "scvtf\ts\[0-9\], x\[0-9\]*.*#32" 1 } } */ + /* { dg-final { scan-assembler-times "ucvtf\ts\[0-9\], x\[0-9\]*.*#32" 1 } } */ + +FUNC_DEFD (32) + /* { dg-final { scan-assembler-times "scvtf\td\[0-9\], w\[0-9\]*.*#32" 1 } } */ + /* { dg-final { scan-assembler-times "ucvtf\td\[0-9\], w\[0-9\]*.*#32" 1 } } */ + /* { dg-final { scan-assembler-times "scvtf\td\[0-9\], x\[0-9\]*.*#32" 1 } } */ + /* { dg-final { scan-assembler-times "ucvtf\td\[0-9\], x\[0-9\]*.*#32" 1 } } */ + +#define FUNC_TESTS(__a, __b) \ +do \ +{ \ + if (fsfoo##__a (__b) != ((int) i) * (1.0f/(1lu << __a)) ) \ + __builtin_abort (); \ + if (fusfoo##__a (__b) != ((int) i) * (1.0f/(1lu << __a)) ) \ + __builtin_abort (); \ + if (fslfoo##__a (__b) != ((int) i) * (1.0f/(1lu << __a)) ) \ + __builtin_abort (); \ + if (fulfoo##__a (__b) != ((int) i) * (1.0f/(1lu << __a)) ) \ + __builtin_abort (); \ +} while (0) + +#define FUNC_TESTD(__a, __b) \ +do \ +{ \ + if (dsfoo##__a (__b) != ((int) i) * (1.0d/(1lu << __a)) ) \ + __builtin_abort (); \ + if (dusfoo##__a (__b) != ((int) i) * (1.0d/(1lu << __a)) ) \ + __builtin_abort (); \ + if (dslfoo##__a (__b) != ((int) i) * (1.0d/(1lu << __a)) ) \ + __builtin_abort (); \ + if (dulfoo##__a (__b) != ((int) i) * (1.0d/(1lu << __a)) ) \ + __builtin_abort (); \ +} while (0) + +int +main (void) +{ + int i; + + for (i = 0; i < 32; i ++) + { + FUNC_TESTS (4, i); + FUNC_TESTS (8, i); + FUNC_TESTS (16, i); + FUNC_TESTS (32, i); + + FUNC_TESTD (4, i); + FUNC_TESTD (8, i); + FUNC_TESTD (16, i); + FUNC_TESTD (32, i); + } + return 0; +} -- 2.17.1