From patchwork Wed Nov 30 10:42:14 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Preudhomme X-Patchwork-Id: 84998 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp169498qgi; Wed, 30 Nov 2016 02:42:47 -0800 (PST) X-Received: by 10.84.213.130 with SMTP id g2mr71547530pli.43.1480502567510; Wed, 30 Nov 2016 02:42:47 -0800 (PST) Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id j62si63824739pfk.288.2016.11.30.02.42.47 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 30 Nov 2016 02:42:47 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-443019-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-443019-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-443019-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:from:message-id:date:mime-version :in-reply-to:content-type; q=dns; s=default; b=K2IHLBjf6F0gMEFxO l0N9XMJoTq8i6NAiChbNfmY4sR55CvYIt+idFtzfVa4XiaiRUaCFxgeXpGsDm05y i5zTWdnkquwZgSNYZ9tZIfBxih6VSbk/o5fLGSMMLfEqsgy+WuIaA+263k/jNyU4 zHERDUrsBr/iaZLkmaR8c3XbN0= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:to:references:from:message-id:date:mime-version :in-reply-to:content-type; s=default; bh=tnvHcztbX/0K8asehaC5UQ4 JPuI=; b=IXGR4n0wvUF+wkk6b0UoAndiB9hrHXXHmXFTfJReAiN+J6UfcWFnVn4 rKyuKdL59saPoXMW6pfCpgGrlnBp3oM93KjGwBO8CtvqB2jKjF90M9Vt7Wk5zbW/ 9fye15saI3D3F08rnP+P4cquiddBNUd5wIIynSoti7CdljGfcWiw= Received: (qmail 54867 invoked by alias); 30 Nov 2016 10:42:28 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 54844 invoked by uid 89); 30 Nov 2016 10:42:27 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.5 required=5.0 tests=BAYES_00, KAM_LAZY_DOMAIN_SECURITY, KAM_LOTSOFHASH, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=UD:pr77904.c, pr77904.c, pr77904c, 77904 X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 30 Nov 2016 10:42:17 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3995816; Wed, 30 Nov 2016 02:42:16 -0800 (PST) Received: from [10.2.206.52] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 775973F318; Wed, 30 Nov 2016 02:42:15 -0800 (PST) Subject: Re: [PATCH, GCC/ARM] Fix PR77904: callee-saved register trashed when clobbering sp To: Kyrill Tkachov , Ramana Radhakrishnan , Richard Earnshaw , "gcc-patches@gcc.gnu.org" References: <582C3541.5080308@foss.arm.com> <7921ba83-b881-8381-04ce-214f9440fc79@foss.arm.com> <582D7435.9090502@foss.arm.com> From: Thomas Preudhomme Message-ID: <7a70eca3-3442-2553-2434-08b5e00879a3@foss.arm.com> Date: Wed, 30 Nov 2016 10:42:14 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.3.0 MIME-Version: 1.0 In-Reply-To: X-IsSubscribed: yes Hi, Is this ok to backport to gcc-5-branch and gcc-6-branch? Patch applies cleanly (patches attached for reference). 2016-11-30 Thomas Preud'homme Backport from mainline 2016-11-22 Thomas Preud'homme gcc/ PR target/77904 * config/arm/arm.c (thumb1_compute_save_reg_mask): Mark frame pointer in save register mask if it is needed. gcc/testsuite/ PR target/77904 * gcc.target/arm/pr77904.c: New test. Best regards, Thomas On 22/11/16 10:45, Thomas Preudhomme wrote: > On 17/11/16 09:11, Kyrill Tkachov wrote: >> >> On 17/11/16 08:56, Thomas Preudhomme wrote: >>> On 16/11/16 10:30, Kyrill Tkachov wrote: >>>> Hi Thomas, >>>> >>>> On 03/11/16 16:52, Thomas Preudhomme wrote: >>>>> Hi, >>>>> >>>>> When using a callee-saved register to save the frame pointer the Thumb-1 >>>>> prologue fails to save the callee-saved register before that. For ARM and >>>>> Thumb-2 targets the frame pointer is handled as a special case but nothing is >>>>> done for Thumb-1 targets. This patch adds the same logic for Thumb-1 targets. >>>>> >>>>> ChangeLog entries are as follow: >>>>> >>>>> *** gcc/ChangeLog *** >>>>> >>>>> 2016-11-02 Thomas Preud'homme >>>>> >>>>> PR target/77904 >>>>> * config/arm/arm.c (thumb1_compute_save_reg_mask): mark frame pointer >>>>> in save register mask if it is needed. >>>>> >>>> >>>> s/mark/Mark/ >>>> >>>>> >>>>> *** gcc/testsuite/ChangeLog *** >>>>> >>>>> 2016-11-02 Thomas Preud'homme >>>>> >>>>> PR target/77904 >>>>> * gcc.target/arm/pr77904.c: New test. >>>>> >>>>> >>>>> Testing: Testsuite shows no regression when run with arm-none-eabi GCC >>>>> cross-compiler for Cortex-M0 target. >>>>> >>>>> Is this ok for trunk? >>>>> >>>> >>>> I'd ask for a bootstrap, but this code is Thumb-1 only so it wouldn't affect >>>> anything. >>> >>> I can bootstrap for armv4t with --with-mode=thumb which would at least >>> exercise the path. I'll try such a bootstrap on qemu. >>> >> >> If you can get it to work, then yes please. > > Bootstrap came back clean so I've committed the patch (r242693). Thanks! > > Best regards, > > Thomas diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 83cb13d1195beb19d6301f5c83a7eb544a91d877..ae479a43fe8514f2eacb7d56f89916b48f720768 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -19390,6 +19390,10 @@ thumb1_compute_save_reg_mask (void) if (df_regs_ever_live_p (reg) && callee_saved_reg_p (reg)) mask |= 1 << reg; + /* Handle the frame pointer as a special case. */ + if (frame_pointer_needed) + mask |= 1 << HARD_FRAME_POINTER_REGNUM; + if (flag_pic && !TARGET_SINGLE_PIC_BASE && arm_pic_register != INVALID_REGNUM diff --git a/gcc/testsuite/gcc.target/arm/pr77904.c b/gcc/testsuite/gcc.target/arm/pr77904.c new file mode 100644 index 0000000000000000000000000000000000000000..76728c07e73350ce44160cabff3dd2fa7a6ef021 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr77904.c @@ -0,0 +1,45 @@ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +__attribute__ ((noinline, noclone)) void +clobber_sp (void) +{ + __asm volatile ("" : : : "sp"); +} + +int +main (void) +{ + int ret; + + __asm volatile ("mov\tr4, #0xf4\n\t" + "mov\tr5, #0xf5\n\t" + "mov\tr6, #0xf6\n\t" + "mov\tr7, #0xf7\n\t" + "mov\tr0, #0xf8\n\t" + "mov\tr8, r0\n\t" + "mov\tr0, #0xfa\n\t" + "mov\tr10, r0" + : : : "r0", "r4", "r5", "r6", "r7", "r8", "r10"); + clobber_sp (); + + __asm volatile ("cmp\tr4, #0xf4\n\t" + "bne\tfail\n\t" + "cmp\tr5, #0xf5\n\t" + "bne\tfail\n\t" + "cmp\tr6, #0xf6\n\t" + "bne\tfail\n\t" + "cmp\tr7, #0xf7\n\t" + "bne\tfail\n\t" + "mov\tr0, r8\n\t" + "cmp\tr0, #0xf8\n\t" + "bne\tfail\n\t" + "mov\tr0, r10\n\t" + "cmp\tr0, #0xfa\n\t" + "bne\tfail\n\t" + "mov\t%0, #1\n" + "fail:\n\t" + "sub\tr0, #1" + : "=r" (ret) : :); + return ret; +}