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Violators will be prosecuted; Tue, 18 Oct 2016 13:47:56 -0600 Received: from b03cxnp07029.gho.boulder.ibm.com (b03cxnp07029.gho.boulder.ibm.com [9.17.130.16]) by d03dlp01.boulder.ibm.com (Postfix) with ESMTP id 375CE1FF0029; Tue, 18 Oct 2016 13:47:36 -0600 (MDT) Received: from b03ledav003.gho.boulder.ibm.com (b03ledav003.gho.boulder.ibm.com [9.17.130.234]) by b03cxnp07029.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id u9IJltEQ15597828; Tue, 18 Oct 2016 12:47:55 -0700 Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B1A896A041; Tue, 18 Oct 2016 13:47:55 -0600 (MDT) Received: from oc1687012634.ibm.com (unknown [9.10.86.67]) by b03ledav003.gho.boulder.ibm.com (Postfix) with ESMTP id 7CE6A6A04C; Tue, 18 Oct 2016 13:47:55 -0600 (MDT) From: Pat Haugen Subject: [PATCH, v2] Fix computation of register limit for -fsched-pressure To: GCC Patches Cc: Maxim Kuvyrkov Date: Tue, 18 Oct 2016 14:47:55 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.4.0 MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Content-Scanned: Fidelis XPS MAILER x-cbid: 16101819-8235-0000-0000-0000096B901A X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00005935; HX=3.00000240; KW=3.00000007; PH=3.00000004; SC=3.00000187; SDB=6.00769905; UDB=6.00368930; IPR=6.00546340; BA=6.00004815; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00013033; XFM=3.00000011; UTC=2016-10-18 19:47:57 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 16101819-8236-0000-0000-000035BE4389 Message-Id: <78d316da-86c9-c618-56d9-839dc07afc4a@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2016-10-18_10:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1609300000 definitions=main-1610180326 X-IsSubscribed: yes The patch here, https://gcc.gnu.org/ml/gcc-patches/2014-10/msg01872.html, attempted to scale down the register limit used by -fsched-pressure for the case where the block in question executes as frequently as the entry block to just the call_clobbered (i.e. call_used) regs. But the code is actually scaling toward call_saved registers. The following patch corrects the following two issues: 1) Computes and then removes the FIXED_REGS for the pressure class. 2) Computes CALL_SAVED regs per class and subtracts out some scaled portion of that. Bootstrap/regtest on powerpc64le in progress. Ok for trunk if no new failures? -Pat 2016-10-18 Pat Haugen * haifa-sched.c (call_used_regs_num): Rename to... (call_saved_regs_num): ...this. (fixed_regs_num): New variable. (sched_pressure_start_bb): Subtract out fixed_regs. Scale call_saved regs not call_used. (alloc_global_sched_pressure_data): Compute call_saved and fixed regs. Index: gcc/haifa-sched.c =================================================================== --- gcc/haifa-sched.c (revision 240569) +++ gcc/haifa-sched.c (working copy) @@ -932,9 +932,10 @@ static bitmap region_ref_regs; /* Effective number of available registers of a given class (see comment in sched_pressure_start_bb). */ static int sched_class_regs_num[N_REG_CLASSES]; -/* Number of call_used_regs. This is a helper for calculating of +/* Number of call_saved_regs and fixed_regs. Helpers for calculating of sched_class_regs_num. */ -static int call_used_regs_num[N_REG_CLASSES]; +static int call_saved_regs_num[N_REG_CLASSES]; +static int fixed_regs_num[N_REG_CLASSES]; /* Initiate register pressure relative info for scheduling the current region. Currently it is only clearing register mentioned in the @@ -3896,17 +3897,19 @@ sched_pressure_start_bb (basic_block bb) * If the basic block executes much more often than the prologue/epilogue (e.g., inside a hot loop), then cost of spill in the prologue is close to nil, so the effective number of available registers is - (ira_class_hard_regs_num[cl] - 0). + (ira_class_hard_regs_num[cl] - fixed_regs_num[cl] - 0). * If the basic block executes as often as the prologue/epilogue, then spill in the block is as costly as in the prologue, so the effective number of available registers is - (ira_class_hard_regs_num[cl] - call_used_regs_num[cl]). + (ira_class_hard_regs_num[cl] - fixed_regs_num[cl] + - call_saved_regs_num[cl]). Note that all-else-equal, we prefer to spill in the prologue, since that allows "extra" registers for other basic blocks of the function. * If the basic block is on the cold path of the function and executes rarely, then we should always prefer to spill in the block, rather than in the prologue/epilogue. The effective number of available register is - (ira_class_hard_regs_num[cl] - call_used_regs_num[cl]). */ + (ira_class_hard_regs_num[cl] - fixed_regs_num[cl] + - call_saved_regs_num[cl]). */ { int i; int entry_freq = ENTRY_BLOCK_PTR_FOR_FN (cfun)->frequency; @@ -3923,9 +3926,10 @@ sched_pressure_start_bb (basic_block bb) for (i = 0; i < ira_pressure_classes_num; ++i) { enum reg_class cl = ira_pressure_classes[i]; - sched_class_regs_num[cl] = ira_class_hard_regs_num[cl]; + sched_class_regs_num[cl] = ira_class_hard_regs_num[cl] + - fixed_regs_num[cl]; sched_class_regs_num[cl] - -= (call_used_regs_num[cl] * entry_freq) / bb_freq; + -= (call_saved_regs_num[cl] * entry_freq) / bb_freq; } } @@ -7237,17 +7241,20 @@ alloc_global_sched_pressure_data (void) region_ref_regs = BITMAP_ALLOC (NULL); } - /* Calculate number of CALL_USED_REGS in register classes that - we calculate register pressure for. */ + /* Calculate number of CALL_SAVED_REGS and FIXED_REGS in register classes + that we calculate register pressure for. */ for (int c = 0; c < ira_pressure_classes_num; ++c) { enum reg_class cl = ira_pressure_classes[c]; - call_used_regs_num[cl] = 0; + call_saved_regs_num[cl] = 0; + fixed_regs_num[cl] = 0; for (int i = 0; i < ira_class_hard_regs_num[cl]; ++i) - if (call_used_regs[ira_class_hard_regs[cl][i]]) - ++call_used_regs_num[cl]; + if (!call_used_regs[ira_class_hard_regs[cl][i]]) + ++call_saved_regs_num[cl]; + else if (fixed_regs[ira_class_hard_regs[cl][i]]) + ++fixed_regs_num[cl]; } } }