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[209.132.180.131]) by mx.google.com with ESMTPS id i67si18561121pfe.129.2019.08.22.07.43.23 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 22 Aug 2019 07:43:23 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-507531-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=fe8PG4er; spf=pass (google.com: domain of gcc-patches-return-507531-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-507531-patch=linaro.org@gcc.gnu.org" DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; q=dns; s=default; b=JhJD6K9mJE8lPik1I3LSBRtvzc8grwQj5x3l06nBdWqNKevMxn 12VIOQeEOslthEboJ7GhU6HPD2wHmIvnV61jdD39ow7kv5vBF4qIjatmhMx8WT8n Ti95S0WfMy7h9D9hiASttOBq50Of8Qm9U3OFdXYZUhE35yYNIyifI5/nc= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; s= default; bh=9n+iGsr/2Fy70Hj3XwLyaWUnjb4=; b=fe8PG4erfc1CUiDGI0yW Yh++2nTnnhZNmeGkkBKrOJ8VualWKd4nyCgwFUulgTu7DsYZcj27D/tFBwHbb6Gp +PqNI2fAd2tBJBqv+NE4z9ULsMBhk4DIkdkRdKGxtexHcYSoTHcwP1c+IJDPMvI7 CrQFFtyNrsQfiXaMyvvL/2s= Received: (qmail 59998 invoked by alias); 22 Aug 2019 14:43:11 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 59983 invoked by uid 89); 22 Aug 2019 14:43:11 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-17.9 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_PASS autolearn=ham version=3.3.1 spammy=ir, Ir X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 22 Aug 2019 14:43:10 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B4B39337; Thu, 22 Aug 2019 07:43:08 -0700 (PDT) Received: from e120077-lin.cambridge.arm.com (e120077-lin.cambridge.arm.com [10.2.206.91]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5FF413F706; Thu, 22 Aug 2019 07:43:08 -0700 (PDT) To: gcc-patches@gcc.gnu.org From: "Richard Earnshaw (lists)" Subject: [Arm] Add 16-bit thumb alternatives to iorsi3_compare0[_scratch] Message-ID: <72ba3f0e-8bbd-0605-a4b7-0aaaffe74124@arm.com> Date: Thu, 22 Aug 2019 15:43:07 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 The iorsi3_compare0 and iorsi3_compare0_scratch patterns can make use of the 16-bit thumb orrs instruction if suitable registers are allocated. This patch adds the alternative to allow this to happen. * config/arm/arm.md (iorsi3_compare0): Add alternative for 16-bit thumb insn. (iorsi3_compare0_scratch): Likewise. Committed to trunk. R. diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 50e1b908f59..4ba246ceeee 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -3339,27 +3339,33 @@ (define_peephole2 (define_insn "*iorsi3_compare0" [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (ior:SI (match_operand:SI 1 "s_register_operand" "%r,r") - (match_operand:SI 2 "arm_rhs_operand" "I,r")) - (const_int 0))) - (set (match_operand:SI 0 "s_register_operand" "=r,r") + (compare:CC_NOOV + (ior:SI (match_operand:SI 1 "s_register_operand" "%r,0,r") + (match_operand:SI 2 "arm_rhs_operand" "I,l,r")) + (const_int 0))) + (set (match_operand:SI 0 "s_register_operand" "=r,l,r") (ior:SI (match_dup 1) (match_dup 2)))] "TARGET_32BIT" "orrs%?\\t%0, %1, %2" [(set_attr "conds" "set") - (set_attr "type" "logics_imm,logics_reg")] + (set_attr "arch" "*,t2,*") + (set_attr "length" "4,2,4") + (set_attr "type" "logics_imm,logics_reg,logics_reg")] ) (define_insn "*iorsi3_compare0_scratch" [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (ior:SI (match_operand:SI 1 "s_register_operand" "%r,r") - (match_operand:SI 2 "arm_rhs_operand" "I,r")) - (const_int 0))) - (clobber (match_scratch:SI 0 "=r,r"))] + (compare:CC_NOOV + (ior:SI (match_operand:SI 1 "s_register_operand" "%r,0,r") + (match_operand:SI 2 "arm_rhs_operand" "I,l,r")) + (const_int 0))) + (clobber (match_scratch:SI 0 "=r,l,r"))] "TARGET_32BIT" "orrs%?\\t%0, %1, %2" [(set_attr "conds" "set") - (set_attr "type" "logics_imm,logics_reg")] + (set_attr "arch" "*,t2,*") + (set_attr "length" "4,2,4") + (set_attr "type" "logics_imm,logics_reg,logics_reg")] ) (define_expand "xordi3"