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[209.132.180.131]) by mx.google.com with ESMTPS id 73si12880748ple.514.2017.07.05.08.34.36 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Jul 2017 08:34:36 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-457630-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.b=uQbSZ5K6; spf=pass (google.com: domain of gcc-patches-return-457630-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-457630-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; q=dns; s=default; b=KLPQEzAR4703Q5qyDvY8za4ZkmFaNFTGoi0X/C7lxE1EwMb7gU e5d+SwNFaWyQc68NHSDn4y8y/wBHP2eJkqLkF4wILNLY/cpnUmIGSqqVvRWbr2Gz +NVK7lTRK1FTnU3g11nbYYk+4twWQdIYK1xZTHYO3p782e6OLlRbmwuzk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to :from:subject:message-id:date:mime-version:content-type; s= default; bh=v1gsNGlNhKGsaz3nXGru38DdDuA=; b=uQbSZ5K6uq5hR3B80Ept EGvgJPEEzLe5FHCLQeAG1znYbGUI0N9G6dRiQRLC8NSXFNfUv5Zv1FPZIkLM1Elf 7RpIlDaYd3AqIDAE63pX5pLRCy2f2dm7lFeTnqf1iHPFg6DFqSMMIbAnfYu0hsEv fnS1lXSwYv55+syafbUCIww= Received: (qmail 6326 invoked by alias); 5 Jul 2017 15:34:24 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 6298 invoked by uid 89); 5 Jul 2017 15:34:23 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 spammy=U*rearnsha, sk:rearnsh X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 05 Jul 2017 15:34:21 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0A52615AD; Wed, 5 Jul 2017 08:34:20 -0700 (PDT) Received: from e105689-lin.cambridge.arm.com (e105689-lin.cambridge.arm.com [10.2.207.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8E6A13F581; Wed, 5 Jul 2017 08:34:19 -0700 (PDT) To: gcc-patches From: "Richard Earnshaw (lists)" Subject: [ARM] Implement TARGET_FIXED_CONDITION_CODE_REGS Message-ID: <5e9f6767-8442-513a-a9ff-cc3673375b3a@arm.com> Date: Wed, 5 Jul 2017 16:34:13 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.1.1 MIME-Version: 1.0 This patch implements TARGET_FIXED_CONDITION_CODE_REGS on ARM. We have two main cases to consider: in Thumb1 code there are no condition code registers, so we simply return false. For other cases we set the the first pointer to CC_REGNUM and the second to VFPCC_REGNUM iff generating hard-float code. Running the CSiBE benchmark I see a couple of cases (both in the same file) where this feature kicks in, so it's not a major change. 2017-07-05 Richard Earnshaw * config/arm/arm.c (arm_fixed_condition_code_regs): New function. (TARGET_FIXED_CONDITION_CODE_REGS): Redefine. Installed on trunk. diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index d3a40b9..c6101ef 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -110,6 +110,7 @@ static void arm_print_operand_address (FILE *, machine_mode, rtx); static bool arm_print_operand_punct_valid_p (unsigned char code); static const char *fp_const_from_val (REAL_VALUE_TYPE *); static arm_cc get_arm_condition_code (rtx); +static bool arm_fixed_condition_code_regs (unsigned int *, unsigned int *); static const char *output_multi_immediate (rtx *, const char *, const char *, int, HOST_WIDE_INT); static const char *shift_op (rtx, HOST_WIDE_INT *); @@ -775,6 +776,9 @@ static const struct attribute_spec arm_attribute_table[] = #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 2 +#undef TARGET_FIXED_CONDITION_CODE_REGS +#define TARGET_FIXED_CONDITION_CODE_REGS arm_fixed_condition_code_regs + /* Obstack for minipool constant handling. */ static struct obstack minipool_obstack; @@ -22928,6 +22932,20 @@ get_arm_condition_code (rtx comparison) return code; } +/* Implement TARGET_FIXED_CONDITION_CODE_REGS. We only have condition + code registers when not targetting Thumb1. The VFP condition register + only exists when generating hard-float code. */ +static bool +arm_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2) +{ + if (!TARGET_32BIT) + return false; + + *p1 = CC_REGNUM; + *p2 = TARGET_HARD_FLOAT ? VFPCC_REGNUM : INVALID_REGNUM; + return true; +} + /* Tell arm_asm_output_opcode to output IT blocks for conditionally executed instructions. */ void