From patchwork Fri Dec 16 12:21:55 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kyrill Tkachov X-Patchwork-Id: 88294 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp1371944qgi; Fri, 16 Dec 2016 04:22:44 -0800 (PST) X-Received: by 10.84.198.129 with SMTP id p1mr6468615pld.14.1481890964598; Fri, 16 Dec 2016 04:22:44 -0800 (PST) Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id n28si7560912pgd.148.2016.12.16.04.22.44 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 16 Dec 2016 04:22:44 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-444586-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-444586-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-444586-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:references :in-reply-to:content-type; q=dns; s=default; b=O/GJiAF8XABCr0HkV WuB1cAWtUOmAcxmFJG0LSPFCp4Oa1nW/TldlG5oT7c/ltfMI+FCnetNOp5t4HLuh ng/wbA7xt69mysxOxIZJ83x48kSs8FYrz0SqpDeCH4ccNExbNs4y0Pvdn/OLVWAa Dw8qPrUUuyA8rg7C40qieXSSwk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:references :in-reply-to:content-type; s=default; bh=e7Dvmi2lEvrFYoClK8Au4nx HX2E=; b=H5JjO+/0nec27+UFOiCyfhoUUk4dehbr/0r2KAEjiVPmIzlR7AkCr58 o3fDUlNh6OYOD3Km7mA8gp8j4SuQT1E3fa5pbS+ZEM8Y2v0D6DyPgHR6hp/5ehVf NxqiGcmF6fHkvbG9F89N3aUSAchh5wW8jlBfMZqmT1j5IcsCgTR4= Received: (qmail 120649 invoked by alias); 16 Dec 2016 12:22:08 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 120620 invoked by uid 89); 16 Dec 2016 12:22:07 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-4.0 required=5.0 tests=BAYES_00, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=gpi, risk, 2016-12-16 X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 16 Dec 2016 12:21:59 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B6980152D; Fri, 16 Dec 2016 04:21:57 -0800 (PST) Received: from [10.2.207.77] (e100706-lin.cambridge.arm.com [10.2.207.77]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D1BD03F445; Fri, 16 Dec 2016 04:21:56 -0800 (PST) Message-ID: <5853DC63.3030602@foss.arm.com> Date: Fri, 16 Dec 2016 12:21:55 +0000 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: James Greenhalgh CC: GCC Patches , Marcus Shawcroft , Richard Earnshaw , nd@arm.com Subject: Re: [PATCH][AArch64] Split X-reg UBFIZ into W-reg LSL when possible References: <5849294D.6040003@foss.arm.com> <20161215115618.GA14881@arm.com> In-Reply-To: <20161215115618.GA14881@arm.com> On 15/12/16 11:56, James Greenhalgh wrote: > On Thu, Dec 08, 2016 at 09:35:09AM +0000, Kyrill Tkachov wrote: >> Hi all, >> >> Similar to the previous patch this transforms X-reg UBFIZ instructions into >> W-reg LSL instructions when the UBFIZ operands add up to 32, so we can take >> advantage of the implicit zero-extension to DImode >> when writing to a W-register. >> >> This is done by splitting the existing *andim_ashift_bfi pattern into >> its two SImode and DImode specialisations and changing the DImode pattern >> into a define_insn_and_split that splits into a >> zero-extended SImode ashift when the operands match up. >> >> So for the code in the testcase we generate: >> LSL W0, W0, 5 >> >> instead of: >> UBFIZ X0, X0, 5, 27 >> >> Bootstrapped and tested on aarch64-none-linux-gnu. >> >> Since we're in stage 3 perhaps this is not for GCC 6, but it is fairly low >> risk. I'm happy for it to wait for the next release if necessary. > My comments on the previous patch also apply here. This patch should only > need to add one new split pattern. > > Thanks, > James Thanks, here is the version adding just a single define_split. Bootstrapped and tested on aarch64-none-linux-gnu. Ok? Thanks, Kyrill 2016-12-16 Kyrylo Tkachov * config/aarch64/aarch64.md: New define_split above bswap2. 2016-12-16 Kyrylo Tkachov * gcc.target/aarch64/ubfiz_lsl_1.c: New test. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 5a40ee6abd5e123116aaaa478dced2207dd59478..b0f7bcbb84159fc8c0c733d0b40f2f08eea241a9 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -4454,6 +4454,24 @@ (define_insn "*andim_ashift_bfiz" [(set_attr "type" "bfx")] ) +;; When the bitposition and width of the equivalent extraction add up to 32 +;; we can use a W-reg LSL instruction taking advantage of the implicit +;; zero-extension of the X-reg. +(define_split + [(set (match_operand:DI 0 "register_operand") + (and:DI (ashift:DI (match_operand:DI 1 "register_operand") + (match_operand 2 "const_int_operand")) + (match_operand 3 "const_int_operand")))] + "aarch64_mask_and_shift_for_ubfiz_p (DImode, operands[3], operands[2]) + && (INTVAL (operands[2]) + popcount_hwi (INTVAL (operands[3]))) + == GET_MODE_BITSIZE (SImode)" + [(set (match_dup 0) + (zero_extend:DI (ashift:SI (match_dup 4) (match_dup 2))))] + { + operands[4] = gen_lowpart (SImode, operands[1]); + } +) + (define_insn "bswap2" [(set (match_operand:GPI 0 "register_operand" "=r") (bswap:GPI (match_operand:GPI 1 "register_operand" "r")))] diff --git a/gcc/testsuite/gcc.target/aarch64/ubfiz_lsl_1.c b/gcc/testsuite/gcc.target/aarch64/ubfiz_lsl_1.c new file mode 100644 index 0000000000000000000000000000000000000000..d3fd3f234f2324d71813298210fdcf0660ac45b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/ubfiz_lsl_1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +/* Check that an X-reg UBFIZ can be simplified into a W-reg LSL. */ + +long long +f2 (long long x) +{ + return (x << 5) & 0xffffffff; +} + +/* { dg-final { scan-assembler "lsl\tw" } } */ +/* { dg-final { scan-assembler-not "ubfiz\tx" } } */