From patchwork Tue Nov 22 09:57:52 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kyrill Tkachov X-Patchwork-Id: 83366 Delivered-To: patch@linaro.org Received: by 10.140.97.165 with SMTP id m34csp2009171qge; Tue, 22 Nov 2016 01:58:23 -0800 (PST) X-Received: by 10.99.240.83 with SMTP id s19mr41795463pgj.175.1479808703044; Tue, 22 Nov 2016 01:58:23 -0800 (PST) Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id x6si27702108pgx.75.2016.11.22.01.58.22 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 22 Nov 2016 01:58:23 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-442201-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-442201-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-442201-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; q=dns; s=default; b=p9gYkHFAJIzKRMkYIF5PjJHr7iuOB6qTKFP1GAqLO8g U13vmsdbofLd1fJhie+JtKr7wR+ZL2X9qE8gorNYPApRy4cuppE6V9X+1RxMb2Rx 7JXtIBPxpC2nYCU5+pjZLyAuFx0Et9+SA+4YtxwxY8jpifi9oFpPDYkoyK0n47yg = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; s=default; bh=wrAK4LeIKjxsPN1m43QAM2G3iJI=; b=VXo4PyNa3cJZ/09Rc GjGw/xkdebXOZGE/4lHh3DmKNe4uOWYXGI0ttfxcPWa0eRslJlGN5JvdK8oK9MCn i/EglsL8rOSUdKpcHj58lGAkJ3X9jgsCNgXnjTx9bEgzzBbJPbFbBxhJ/8hjjUj3 J7Hfdk8BfLziYyXYGeer1tvYto= Received: (qmail 19849 invoked by alias); 22 Nov 2016 09:58:08 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 19819 invoked by uid 89); 22 Nov 2016 09:58:06 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.9 required=5.0 tests=BAYES_00, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=sk:output_, 2016-11-22 X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 22 Nov 2016 09:57:56 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A1F1A28; Tue, 22 Nov 2016 01:57:54 -0800 (PST) Received: from [10.2.207.77] (e100706-lin.cambridge.arm.com [10.2.207.77]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0F6713F483; Tue, 22 Nov 2016 01:57:53 -0800 (PST) Message-ID: <583416A0.9010402@foss.arm.com> Date: Tue, 22 Nov 2016 09:57:52 +0000 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: GCC Patches CC: Ramana Radhakrishnan , Richard Earnshaw Subject: [PATCH][ARM] PR target/78439: Update movdi constraints for Cortex-A8 tuning to handle LDRD/STRD Hi all, This PR is an ICE while bootstrapping GCC with Cortex-A8 tuning, which we also get from the default ARMv7-A tuning. The ldrd/strd peepholes were recently made more aggressive and in this case they transform: (insn 13 33 40 2 (set (mem/c:SI (plus:SI (reg/f:SI 11 fp) (const_int -28 [0xffffffffffffffe4])) [3 d.num_comps+0 S4 A64]) (reg:SI 12 ip [orig:117 _20 ] [117])) "cp-demangle.c":32 632 {*arm_movsi_vfp} (expr_list:REG_DEAD (reg:SI 12 ip [orig:117 _20 ] [117]) (nil))) (insn 40 13 39 2 (set (mem/f/c:SI (plus:SI (reg/f:SI 11 fp) (const_int -24 [0xffffffffffffffe8])) [2 d.subs+0 S4 A32]) (reg/f:SI 13 sp)) "cp-demangle.c":51 632 {*arm_movsi_vfp} (nil)) into: (insn 68 33 39 2 (set (mem/c:DI (plus:SI (reg/f:SI 11 fp) (const_int -28 [0xffffffffffffffe4])) [3 d.num_comps+0 S8 A64]) (reg:DI 12 ip)) "cp-demangle.c":51 -1 (nil)) This is okay, but the *movdi_vfp_cortexa8 pattern doesn't deal with the IP being the source of the store. The reason is that when the LDRD/STRD peepholes and machinery was introduced back in r197530 it created the 'q' constraint which should be used for the register operands of the DImode stores and loads ('q' means CORE_REGS when LDRD/STRD is enabled in ARM mode and GENERAL_REGS otherwise). That revision updated the movdi_vfp pattern to use it in alternatives 4,5,6 but neglected to udpate the Cortex-A8-specific pattern. This is a sign that we should perhaps get rid of this special-cased pattern at some point, but for now this simple patch updates the appropriate alternatives to use the 'q' constraint so that output_move_double can output the correct LDRD/STRD instruction. Bootstrapped on arm-none-linux-gnueabihf with --with-arch=armv7-a that exercises this code (bootstrap currently fails without this patch) and tested with /-mtune=cortex-a8. Ok for trunk? Thanks, Kyrill 2016-11-22 Kyrylo Tkachov PR target/78439 * config/arm/vfp.md (*movdi_vfp_cortexa8): Use 'q' constraints for the register operand in alternatives 4,5,6. 2016-11-22 Kyrylo Tkachov PR target/78439 * gcc.c-torture/compile/pr78439.c: New test. commit 600526ea992fa58f87e6b0b4f821f4a2dfd0fa7a Author: Kyrylo Tkachov Date: Mon Nov 21 12:00:20 2016 +0000 [ARM] PR target/78439: Update movdi constraints for Cortex-A8 tuning to handled LDRD/STRD diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index 2051f10..ce56e16 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -355,8 +355,8 @@ (define_insn "*movdi_vfp" ) (define_insn "*movdi_vfp_cortexa8" - [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,r,r,r,r,m,w,!r,w,w, Uv") - (match_operand:DI 1 "di_operand" "r,rDa,Db,Dc,mi,mi,r,r,w,w,Uvi,w"))] + [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,r,r,q,q,m,w,!r,w,w, Uv") + (match_operand:DI 1 "di_operand" "r,rDa,Db,Dc,mi,mi,q,r,w,w,Uvi,w"))] "TARGET_32BIT && TARGET_HARD_FLOAT && arm_tune == TARGET_CPU_cortexa8 && ( register_operand (operands[0], DImode) || register_operand (operands[1], DImode)) diff --git a/gcc/testsuite/gcc.c-torture/compile/pr78439.c b/gcc/testsuite/gcc.c-torture/compile/pr78439.c new file mode 100644 index 0000000..a8af86b --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/compile/pr78439.c @@ -0,0 +1,56 @@ +/* PR target/78439. */ + +enum demangle_component_type +{ + DEMANGLE_COMPONENT_THROW_SPEC +}; +struct demangle_component +{ + enum demangle_component_type type; + struct + { + struct + { + struct demangle_component *left; + struct demangle_component *right; + }; + }; +}; + +int a, b; + +struct d_info +{ + struct demangle_component *comps; + int next_comp; + int num_comps; + struct demangle_component *subs; + int num_subs; + int is_conversion; +}; + +void +fn1 (int p1, struct d_info *p2) +{ + p2->num_comps = 2 * p1; + p2->next_comp = p2->num_subs = p1; + p2->is_conversion = 0; +} + +int fn3 (int *); +void fn4 (struct d_info *, int); + +void +fn2 () +{ + int c; + struct d_info d; + b = 0; + c = fn3 (&a); + fn1 (c, &d); + struct demangle_component e[d.num_comps]; + struct demangle_component *f[d.num_subs]; + d.comps = e; + d.subs = (struct demangle_component *) f; + fn4 (&d, 1); +}