From patchwork Thu Nov 3 12:05:33 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kyrill Tkachov X-Patchwork-Id: 80644 Delivered-To: patch@linaro.org Received: by 10.140.97.247 with SMTP id m110csp595186qge; Thu, 3 Nov 2016 05:05:52 -0700 (PDT) X-Received: by 10.99.251.69 with SMTP id w5mr13483908pgj.108.1478174752831; Thu, 03 Nov 2016 05:05:52 -0700 (PDT) Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id d123si9293851pgc.184.2016.11.03.05.05.52 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Nov 2016 05:05:52 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-440293-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-440293-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-440293-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:references :in-reply-to:content-type; q=dns; s=default; b=J5F/7dX793NCPJazA U8xzayB5YuGegcDdeJyeN4oHo29fgTFd317m40gF2PC7MSDNfbu+b/zJjZZ30L/J XhOJY7ZH9VijUB8fS1daHBZekCYNoj9lnbSDkuFAoIwmstxLVuKHfImBaRfVemcn XSuuIrq+FmHoM1loJtEHLUfsDE= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:references :in-reply-to:content-type; s=default; bh=18bru9yT7xefpVh7n0aKbMt 5Y2A=; b=pixlvYWMD/A+S7YK+kKsvVAmDijSFHXBsd/AmnpbKcIfs+PlbvsAvm7 54fLprZ9zH1JovNg6JXr3iyQZCLNLWJE+yu/vKVk+QOzEmsw4q7SvPXro2a63LEw 46sXaVOtrbw1V7hJM9krPWQrCN7Sc5i9bP2Np56kF9nNV+4K0gqo= Received: (qmail 77834 invoked by alias); 3 Nov 2016 12:05:39 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 77815 invoked by uid 89); 3 Nov 2016 12:05:38 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.2 required=5.0 tests=BAYES_00, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=Hx-languages-length:2785 X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 03 Nov 2016 12:05:37 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 70AD116; Thu, 3 Nov 2016 05:05:35 -0700 (PDT) Received: from [10.2.207.77] (e100706-lin.cambridge.arm.com [10.2.207.77]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 01DED3F220; Thu, 3 Nov 2016 05:05:34 -0700 (PDT) Message-ID: <581B280D.4080401@foss.arm.com> Date: Thu, 03 Nov 2016 12:05:33 +0000 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: Eric Botcazou CC: gcc-patches@gcc.gnu.org Subject: Re: [PATCH][rtlanal.c] Convert conditional compilation on WORD_REGISTER_OPERATIONS References: <56704D17.4030103@foss.arm.com> <14940682.LInKzSekam@polaris> <5819CB01.3080707@foss.arm.com> <2203551.UJeNYAYk4T@polaris> In-Reply-To: <2203551.UJeNYAYk4T@polaris> On 02/11/16 11:36, Eric Botcazou wrote: >> I think you're right. I suppose the new condition should be: >> >> #ifdef LOAD_EXTEND_OP >> /* If this is a typical RISC machine, we only have to worry >> about the way loads are extended. */ >> if (!WORD_REGISTER_OPERATIONS >> >> || ((LOAD_EXTEND_OP (inner_mode) == SIGN_EXTEND >> >> ? val_signbit_known_set_p (inner_mode, nonzero) >> >> : LOAD_EXTEND_OP (inner_mode) != ZERO_EXTEND) >> || >> || !MEM_P (SUBREG_REG (x)))) >> >> #endif > Agreed. > >> Would you prefer me to make this change or just revert the patch? > Go ahead and make the change, but please do a bit of comment massaging in the > process, for example: > > #ifdef LOAD_EXTEND_OP > /* On many CISC machines, accessing an object in a wider mode > causes the high-order bits to become undefined. So they are > not known to be zero. */ > if (!WORD_REGISTER_OPERATIONS > /* If this is a typical RISC machine, we only have to worry > about the way loads are extended. */ > || ((LOAD_EXTEND_OP (inner_mode) == SIGN_EXTEND > ? val_signbit_known_set_p (inner_mode, nonzero) > : LOAD_EXTEND_OP (inner_mode) != ZERO_EXTEND) > || !MEM_P (SUBREG_REG (x)))) > #endif > { > if (GET_MODE_PRECISION (GET_MODE (x)) > > GET_MODE_PRECISION (inner_mode)) > nonzero |= (GET_MODE_MASK (GET_MODE (x)) > & ~GET_MODE_MASK (inner_mode)); > } > Thanks, here is the patch doing this. Committing to trunk after bootstrap and testing on x86_64. Sorry for the trouble, Kyrill diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c index 9107af0fda76fe2233bc5cf1e439b9971d6691f0..b655315f380f221abcf9176635441688d1756b1e 100644 --- a/gcc/rtlanal.c +++ b/gcc/rtlanal.c @@ -4568,18 +4568,18 @@ nonzero_bits1 (const_rtx x, machine_mode mode, const_rtx known_x, known_x, known_mode, known_ret); #ifdef LOAD_EXTEND_OP - /* If this is a typical RISC machine, we only have to worry - about the way loads are extended. */ - if (WORD_REGISTER_OPERATIONS - && ((LOAD_EXTEND_OP (inner_mode) == SIGN_EXTEND + /* On many CISC machines, accessing an object in a wider mode + causes the high-order bits to become undefined. So they are + not known to be zero. */ + if (!WORD_REGISTER_OPERATIONS + /* If this is a typical RISC machine, we only have to worry + about the way loads are extended. */ + || ((LOAD_EXTEND_OP (inner_mode) == SIGN_EXTEND ? val_signbit_known_set_p (inner_mode, nonzero) : LOAD_EXTEND_OP (inner_mode) != ZERO_EXTEND) || !MEM_P (SUBREG_REG (x)))) #endif { - /* On many CISC machines, accessing an object in a wider mode - causes the high-order bits to become undefined. So they are - not known to be zero. */ if (GET_MODE_PRECISION (GET_MODE (x)) > GET_MODE_PRECISION (inner_mode)) nonzero |= (GET_MODE_MASK (GET_MODE (x))