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[70.176.202.128]) by smtp.googlemail.com with ESMTPSA id fn3sm34274105pab.20.2016.02.28.20.47.27 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 28 Feb 2016 20:47:27 -0800 (PST) To: GCC Patches , Kyrill Tkachov , Ramana Radhakrishnan From: Michael Collison Subject: [PATCH][ARM] PR target/70008 Message-ID: <56D3CD4F.6060301@linaro.org> Date: Sun, 28 Feb 2016 21:47:11 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 MIME-Version: 1.0 This patches address PR 70008, where a reverse subtract with carry instruction can be generated in thumb2 mode. It was tested with no regressions in arm and thumb modes on the following targets: arm-none-linux-gnueabi arm-none-linux-gnuabihf armeb-none-linux-gnuabihf arm-none-eabi Okay for trunk? 2016-02-28 Michael Collison PR target/70008 * config/arm/arm.md (*subsi3_carryin): Only match pattern if TARGET_ARM due to 'rsc' instruction alternative. * config/arm/thumb2.md (*thumb2_subsi3_carryin): New pattern. -- Michael Collison Linaro Toolchain Working Group michael.collison@linaro.org diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index e67239d..a008207 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -870,7 +870,7 @@ (minus:SI (minus:SI (match_operand:SI 1 "reg_or_int_operand" "r,I") (match_operand:SI 2 "s_register_operand" "r,r")) (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] - "TARGET_32BIT" + "TARGET_ARM" "@ sbc%?\\t%0, %1, %2 rsc%?\\t%0, %2, %1" diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index 9925365..79305c5 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -848,6 +848,20 @@ (set_attr "type" "multiple")] ) +(define_insn "*thumb2_subsi3_carryin" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (minus:SI (minus:SI (match_operand:SI 1 "s_register_operand" "r") + (match_operand:SI 2 "s_register_operand" "r")) + (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] + "TARGET_THUMB2" + "@ + sbc%?\\t%0, %1, %2" + [(set_attr "conds" "use") + (set_attr "predicable" "yes") + (set_attr "predicable_short_it" "no") + (set_attr "type" "adc_reg")] +) + (define_insn "*thumb2_cond_sub" [(set (match_operand:SI 0 "s_register_operand" "=Ts,Ts") (minus:SI (match_operand:SI 1 "s_register_operand" "0,?Ts") -- 1.9.1