From patchwork Fri Dec 4 09:30:45 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kyrylo Tkachov X-Patchwork-Id: 57703 Delivered-To: patch@linaro.org Received: by 10.112.155.196 with SMTP id vy4csp435057lbb; Fri, 4 Dec 2015 01:31:10 -0800 (PST) X-Received: by 10.66.234.133 with SMTP id ue5mr20169708pac.56.1449221469943; Fri, 04 Dec 2015 01:31:09 -0800 (PST) Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id s20si18338921pfa.146.2015.12.04.01.31.09 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 04 Dec 2015 01:31:09 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-416350-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-return-416350-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-416350-patch=linaro.org@gcc.gnu.org; dkim=pass header.i=@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; q=dns; s=default; b=EgVVOT9Fqvi/UQ//JuyUNEoXX7h86PI5ijOPhCInfNl cGrLOoO6kzTXoaFbKAzIkEXMqetxlBLtVC0+KrPkwiTsY/0eP06KzzeD2kka9d/A 48u/I1BCzyD83pW2iVvmf4T91bxVT4dOazCqfthIS403bk7fKO1uCCbFhOjGnlyw = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; s=default; bh=7JOAmsOuOV3JPv9S48HeTvUyVXM=; b=B15zRmz+QxwQXC3+9 P0LIexb9ylLZWPOkVQbceIr/Nl9kH6HworehE7T7tR4Fy0E1o0zmTAq+JwZHagwB XyGgfET9RVozESLGbt8pf046PwNar6r7xiILztbG+WMWb8O0Lb3ZzAnWbPx+LT+O IixBAyApaEDwkY6EjRaLtqBbM8= Received: (qmail 63905 invoked by alias); 4 Dec 2015 09:30:56 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 63820 invoked by uid 89); 4 Dec 2015 09:30:56 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (146.101.78.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 04 Dec 2015 09:30:52 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-5-L-rHxSB8QrmnWZgRFVz1yQ-1; Fri, 04 Dec 2015 09:30:47 +0000 Received: from [10.2.206.200] ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 4 Dec 2015 09:30:47 +0000 Message-ID: <56615D45.80408@arm.com> Date: Fri, 04 Dec 2015 09:30:45 +0000 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: GCC Patches CC: Marcus Shawcroft , Richard Earnshaw , James Greenhalgh Subject: [PATCH][AArch64] Properly cost zero_extend+ashift forms of ubfi[xz] X-MC-Unique: L-rHxSB8QrmnWZgRFVz1yQ-1 X-IsSubscribed: yes Hi all, We don't handle properly the patterns for the [us]bfiz and [us]bfx instructions when they have an extend+ashift form. For example, the *_ashl pattern. This leads to rtx costs recuring into the extend and assigning a cost to these patterns that is too large. This patch fixes that oversight. I stumbled across this when working on a different combine patch and ended up matching the above pattern, only to have it rejected for -mcpu=cortex-a53 due to the erroneous cost. Bootstrapped and tested on aarch64. Ok for trunk? Thanks, Kyrill 2015-12-04 Kyrylo Tkachov * config/aarch64/aarch64.c (aarch64_extend_bitfield_pattern_p): New function. (aarch64_rtx_costs, ZERO_EXTEND, SIGN_EXTEND cases): Use the above to handle extend+shift rtxes. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index c97ecdc0859e0a24792a57aeb18b2e4ea35918f4..d180f6f2d37a280ad77f34caad8496ddaa6e01b2 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -5833,6 +5833,50 @@ aarch64_if_then_else_costs (rtx op0, rtx op1, rtx op2, int *cost, bool speed) return false; } +/* Check whether X is a bitfield operation of the form shift + extend that + maps down to a UBFIZ/SBFIZ/UBFX/SBFX instruction. If so, return the + operand to which the bitfield operation is applied to. Otherwise return + NULL_RTX. */ + +static rtx +aarch64_extend_bitfield_pattern_p (rtx x) +{ + rtx_code outer_code = GET_CODE (x); + machine_mode outer_mode = GET_MODE (x); + + if (outer_code != ZERO_EXTEND && outer_code != SIGN_EXTEND + && outer_mode != SImode && outer_mode != DImode) + return NULL_RTX; + + rtx inner = XEXP (x, 0); + rtx_code inner_code = GET_CODE (inner); + machine_mode inner_mode = GET_MODE (inner); + rtx op = NULL_RTX; + + switch (inner_code) + { + case ASHIFT: + if (CONST_INT_P (XEXP (inner, 1)) + && (inner_mode == QImode || inner_mode == HImode)) + op = XEXP (inner, 0); + break; + case LSHIFTRT: + if (outer_code == ZERO_EXTEND && CONST_INT_P (XEXP (inner, 1)) + && (inner_mode == QImode || inner_mode == HImode)) + op = XEXP (inner, 0); + break; + case ASHIFTRT: + if (outer_code == SIGN_EXTEND && CONST_INT_P (XEXP (inner, 1)) + && (inner_mode == QImode || inner_mode == HImode)) + op = XEXP (inner, 0); + break; + default: + break; + } + + return op; +} + /* Calculate the cost of calculating X, storing it in *COST. Result is true if the total cost of the operation has now been calculated. */ static bool @@ -6521,6 +6565,14 @@ cost_plus: return true; } + op0 = aarch64_extend_bitfield_pattern_p (x); + if (op0) + { + *cost += rtx_cost (op0, mode, ZERO_EXTEND, 0, speed); + if (speed) + *cost += extra_cost->alu.bfx; + return true; + } if (speed) { if (VECTOR_MODE_P (mode)) @@ -6552,6 +6604,14 @@ cost_plus: return true; } + op0 = aarch64_extend_bitfield_pattern_p (x); + if (op0) + { + *cost += rtx_cost (op0, mode, SIGN_EXTEND, 0, speed); + if (speed) + *cost += extra_cost->alu.bfx; + return true; + } if (speed) { if (VECTOR_MODE_P (mode))