From patchwork Mon Nov 9 11:32:33 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kyrylo Tkachov X-Patchwork-Id: 56216 Delivered-To: patch@linaro.org Received: by 10.112.155.196 with SMTP id vy4csp125150lbb; Mon, 9 Nov 2015 03:32:52 -0800 (PST) X-Received: by 10.68.102.33 with SMTP id fl1mr39138462pbb.40.1447068772689; Mon, 09 Nov 2015 03:32:52 -0800 (PST) Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id uv8si21900661pbc.187.2015.11.09.03.32.52 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 09 Nov 2015 03:32:52 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-413218-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-return-413218-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-413218-patch=linaro.org@gcc.gnu.org; dkim=pass header.i=@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; q=dns; s=default; b=BFmeYLz/9gil5Hpkzi9DWr99M3duW7uoWHCInQ69yev bwqiTJodAkBpr78fuOW6SHQPuZ2zMBBwaXNKLQkT7kaRwuxfznXBKtzgdT+KV5Y2 RIKwetdqhGgBpyusj1dBcxVEGy6aa5sMnciKWgI/dvsa2/jKgynLCZJiCjJcArj8 = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; s=default; bh=zD8XzN/mBqCSHgd4qXD0RWIaM8s=; b=yP6oScqhPv9DQw+al m4HDgrySRp574Nej/Rwl3serlFYCtPbZScu1ZTn5Ima7cjkA7R9gz9K6SI9cXHOa eN8HOjBIelBLnowOs6ZLd2w2dAQj8s/AmG/+++sK0wTo2b/y4sdYU1TawB9CbOBN GBfLvq5Z821lvEcFqcKnAaZrdY= Received: (qmail 7272 invoked by alias); 9 Nov 2015 11:32:40 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 7258 invoked by uid 89); 9 Nov 2015 11:32:39 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (146.101.78.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 09 Nov 2015 11:32:38 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-5-Sd_tQO6WSr-HJmb2MIEzTw-1; Mon, 09 Nov 2015 11:32:33 +0000 Received: from [10.2.206.200] ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 9 Nov 2015 11:32:33 +0000 Message-ID: <56408451.6010502@arm.com> Date: Mon, 09 Nov 2015 11:32:33 +0000 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: GCC Patches CC: Marcus Shawcroft , Richard Earnshaw , James Greenhalgh Subject: [PATCH][AArch64] PR target/68129: Define TARGET_SUPPORTS_WIDE_INT X-MC-Unique: Sd_tQO6WSr-HJmb2MIEzTw-1 X-IsSubscribed: yes Hi all, In this PR we hit an ICE in simplify-rtx.c: #if TARGET_SUPPORTS_WIDE_INT == 0 /* This assert keeps the simplification from producing a result that cannot be represented in a CONST_DOUBLE but a lot of upstream callers expect that this function never fails to simplify something and so you if you added this to the test above the code would die later anyway. If this assert happens, you just need to make the port support wide int. */ gcc_assert (width <= HOST_BITS_PER_DOUBLE_INT); #endif The aarch64 port does not define TARGET_SUPPORTS_WIDE_INT. From what I understand, in order to define it we need to remove the instances in the backend where we use CONST_DOUBLE rtxes with VOIDmode (i.e. for storing CONST_INTs). From what I can see we don't create such instances, so this patch defines TARGET_SUPPORTS_WIDE_INT and cleans up a couple of places in the backend that try to hypothetically handle CONST_DOUBLEs as CONST_INTs if they are passed down as such from other places in the compiler. Bootstrapped and tested on aarch64-none-linux-gnu on trunk and GCC 5. No codegen differences on SPEC2006. Ok for trunk and GCC 5? Thanks, Kyrill 2015-11-09 Kyrylo Tkachov PR target/68129 * config/aarch64/aarch64.h (TARGET_SUPPORTS_WIDE_INT): Define to 1. * config/aarch64/aarch64.c (aarch64_print_operand, CONST_DOUBLE): Delete VOIDmode case. Assert that mode is not VOIDmode. * config/aarch64/predicates.md (const0_operand): Remove const_double match. 2015-11-09 Kyrylo Tkachov PR target/68129 * gcc.target/aarch64/pr68129_1.c: New test. commit 10562c44766a57e4762e926f876f5457f9899e33 Author: Kyrylo Tkachov Date: Wed Oct 28 10:49:44 2015 +0000 [AArch64] PR target/68129: Define TARGET_SUPPORTS_WIDE_INT diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 47ccc32..389bfc0 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -4401,11 +4401,10 @@ aarch64_print_operand (FILE *f, rtx x, char code) break; case CONST_DOUBLE: - /* CONST_DOUBLE can represent a double-width integer. - In this case, the mode of x is VOIDmode. */ - if (GET_MODE (x) == VOIDmode) - ; /* Do Nothing. */ - else if (aarch64_float_const_zero_rtx_p (x)) + /* Since we define TARGET_SUPPORTS_WIDE_INT we shouldn't ever + be getting CONST_DOUBLEs holding integers. */ + gcc_assert (GET_MODE (x) != VOIDmode); + if (aarch64_float_const_zero_rtx_p (x)) { fputc ('0', f); break; diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index b041a1e..0fac0a7 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -863,6 +863,8 @@ extern enum aarch64_code_model aarch64_cmodel; (aarch64_cmodel == AARCH64_CMODEL_TINY \ || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC) +#define TARGET_SUPPORTS_WIDE_INT 1 + /* Modes valid for AdvSIMD D registers, i.e. that fit in half a Q register. */ #define AARCH64_VALID_SIMD_DREG_MODE(MODE) \ ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md index 1bcbf62..8775460 100644 --- a/gcc/config/aarch64/predicates.md +++ b/gcc/config/aarch64/predicates.md @@ -32,7 +32,7 @@ (define_predicate "aarch64_call_insn_operand" ;; Return true if OP a (const_int 0) operand. (define_predicate "const0_operand" - (and (match_code "const_int, const_double") + (and (match_code "const_int") (match_test "op == CONST0_RTX (mode)"))) (define_predicate "aarch64_ccmp_immediate" diff --git a/gcc/testsuite/gcc.target/aarch64/pr68129_1.c b/gcc/testsuite/gcc.target/aarch64/pr68129_1.c new file mode 100644 index 0000000..112331e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr68129_1.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O -fno-split-wide-types" } */ + +typedef int V __attribute__ ((vector_size (8 * sizeof (int)))); + +void +foo (V *p, V *q) +{ + *p = (*p == *q); +}