From patchwork Tue Oct 27 18:06:12 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kyrylo Tkachov X-Patchwork-Id: 55648 Delivered-To: patch@linaro.org Received: by 10.112.59.35 with SMTP id w3csp1945307lbq; Tue, 27 Oct 2015 11:06:30 -0700 (PDT) X-Received: by 10.66.161.35 with SMTP id xp3mr29439245pab.13.1445969190851; Tue, 27 Oct 2015 11:06:30 -0700 (PDT) Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id wp3si63447519pab.160.2015.10.27.11.06.30 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 27 Oct 2015 11:06:30 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-411719-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-return-411719-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-411719-patch=linaro.org@gcc.gnu.org; dkim=pass header.i=@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; q=dns; s=default; b=uXmmaxWE3buNZuCFVRJa2VI12T+gHNtUoJI8hyZeJIW zsQXI1xaNfRQR4GaRDhUsPlR/2YyuP3ZGtuZyy7IWah/qXb6EfYcvS3Xsm3VdCnL OzdQa+yrda4nocXfUT9bZViR9KgkwjcHWpH7Br8SzawFCBkStbRMCyJZ4nPn3p5s = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; s=default; bh=xdzttpOaRWnCrj6lL7ckC9/sL9A=; b=hrifQl3XPs8S2CYwH 5sP3G/lqIq5T7o3K6q9XvVIP/GF08rFmLYwQnkmXx3IswrPv7CDVjVKNafd/8Bpy ztqM/hEA+mTgOsBaupA6PzUCmfkkztyhLLTOgyHjs7Xu4vIUjCspNd14Xtkyb6VG 1U0uc+bR+TLSo+E6BtarxxW2Ec= Received: (qmail 31619 invoked by alias); 27 Oct 2015 18:06:19 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 31608 invoked by uid 89); 27 Oct 2015 18:06:19 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (207.82.80.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 27 Oct 2015 18:06:17 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-22-GEZuBHz6Q8WOQtIjyx22Rg-1; Tue, 27 Oct 2015 18:06:12 +0000 Received: from [10.2.207.50] ([10.1.2.79]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 27 Oct 2015 18:06:12 +0000 Message-ID: <562FBD14.3050105@arm.com> Date: Tue, 27 Oct 2015 18:06:12 +0000 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: GCC Patches CC: Marcus Shawcroft , Richard Earnshaw , James Greenhalgh Subject: [PATCH][AArch64] PR 68102: Check that operand is REG before checking the REGNO in mov-immediate splitters X-MC-Unique: GEZuBHz6Q8WOQtIjyx22Rg-1 X-IsSubscribed: yes Hi all, This is another RTL checking error occuring in the splitting condition of the mov-immediate patterns. We take a REGNO of operands[0] which is a nonimmediate_operand. Since the immediate splitting code only makes sense when the destination is a register, we should be guarding that condition on REG_P (operands[0]). The reported error occurs on the *movdi_aarch64 pattern but I see the same vulnerability in the *movsi_aarch64 pattern, although I wasn't able to get it to trigger an ICE. This patch adds a REG_P check on the splitting condition of both. The testcase (taken from the BZ for PR 68102 and with an #if 1 removed)now compiles fine on an aarch64 compiler with RTL checking enabled. Bootstrapped and tested on aarch64-linux with RTL checking enabled. Ok for trunk? Thanks, Kyrill The BZ says this occurs on the GCC 5 branch but I don't have a checking compiler from that branch yet. I'll be investigating whether to backport this patch there in the meantime. 2015-10-27 Kyrylo Tkachov PR target/68102 * config/aarch64/aarch64.md (*movsi_aarch64): Check that operands[0] is a reg before taking its REGNO in split condition. (*movdi_aarch64): Likewise. 2015-10-27 Kyrylo Tkachov PR target/68102 * gcc.target/aarch64/pr68102_1.c: New test. commit 60e037bdc67949abe2589a91a80afd67c9b13926 Author: Kyrylo Tkachov Date: Tue Oct 27 12:18:22 2015 +0000 [AArch64] PR 68102: Check that operand is REG before checking the REGNO in mov-immediate splitters diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 77df46f..0cb64ee 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -1031,7 +1031,7 @@ (define_insn_and_split "*movsi_aarch64" fmov\\t%w0, %s1 fmov\\t%s0, %s1" "CONST_INT_P (operands[1]) && !aarch64_move_imm (INTVAL (operands[1]), SImode) - && GP_REGNUM_P (REGNO (operands[0]))" + && REG_P (operands[0]) && GP_REGNUM_P (REGNO (operands[0]))" [(const_int 0)] "{ aarch64_expand_mov_immediate (operands[0], operands[1]); @@ -1064,7 +1064,7 @@ (define_insn_and_split "*movdi_aarch64" fmov\\t%d0, %d1 movi\\t%d0, %1" "(CONST_INT_P (operands[1]) && !aarch64_move_imm (INTVAL (operands[1]), DImode)) - && GP_REGNUM_P (REGNO (operands[0]))" + && REG_P (operands[0]) && GP_REGNUM_P (REGNO (operands[0]))" [(const_int 0)] "{ aarch64_expand_mov_immediate (operands[0], operands[1]); diff --git a/gcc/testsuite/gcc.target/aarch64/pr68102_1.c b/gcc/testsuite/gcc.target/aarch64/pr68102_1.c new file mode 100644 index 0000000..3193b27 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr68102_1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +typedef __Float64x1_t float64x1_t; + +typedef long int64_t; + +extern int64_t bar (float64x1_t f); + +int +foo (void) +{ + float64x1_t f = { 3.14159265358979311599796346854 }; + int64_t c = 0x400921FB54442D18; + int64_t r; + r = bar (f); + return r == c; +}