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[209.132.180.131]) by mx.google.com with ESMTPS id i6si2238119igi.84.2015.09.25.05.53.54 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 25 Sep 2015 05:53:55 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-408323-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 27082 invoked by alias); 25 Sep 2015 12:53:42 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 27068 invoked by uid 89); 25 Sep 2015 12:53:41 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (207.82.80.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 25 Sep 2015 12:53:40 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-26-xZQcXsjtT02TpOLlFV4uKQ-1; Fri, 25 Sep 2015 13:53:36 +0100 Received: from [10.2.207.50] ([10.1.2.79]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 25 Sep 2015 13:53:36 +0100 Message-ID: <560543CF.2000909@arm.com> Date: Fri, 25 Sep 2015 13:53:35 +0100 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: James Greenhalgh , "gcc-patches@gcc.gnu.org" CC: Marcus Shawcroft , Richard Earnshaw , Ramana Radhakrishnan Subject: Re: [Patch 1/2 AArch64/ARM] Give AArch64 ROR (Immediate) a new type attribute References: <1443167973-37806-1-git-send-email-james.greenhalgh@arm.com> <1443167973-37806-2-git-send-email-james.greenhalgh@arm.com> In-Reply-To: <1443167973-37806-2-git-send-email-james.greenhalgh@arm.com> X-MC-Unique: xZQcXsjtT02TpOLlFV4uKQ-1 X-IsSubscribed: yes X-Original-Sender: kyrylo.tkachov@arm.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c03::233 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 Hi James, On 25/09/15 08:59, James Greenhalgh wrote: > Hi, > > This patch splits the "shift_imm" type attribute used by AArch64 in > two - giving rotate_imm and shift_imm. > > We then apply this transform across the AArch64 pipeline descriptions > which have modelling for shift_imm (cortex-a53, cortex-a57, thunderx). > This should give no functional change to these models. > > Bootstrapped and tested on aarch64-none-linux-gnu, and > arm-none-linux-gnueabihf with no issues. > > OK? > > Thanks, > James > > --- > 2015-09-25 James Greenhalgh > > * config/arm/types.md (type): Add rotate_imm. > * config/aarch64/aarch64.md (*ror3_insn): Split out the > ROR immediate case. > (*rorsi3_insn_uxtw): Likewise. > * config/aarch64/thunderx.md (thunderx_shift): Add rotate_imm. > * config/arm/cortex-a53.md (cortex_a53_alu_shift): Add rotate_imm. > * config/arm/cortex-a57.md (cortex_a53_alu): Add rotate_imm. > identical output templates using '@'. You can just specify the alternative values for the "type" attribute. See the *sub_shiftsi pattern in the arm backend for an example of that. arm-wise this patch is ok since you don't actually introduce usage of the new type to any arm patterns. Thanks, Kyrill --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3807,13 +3807,15 @@ ;; Rotate right (define_insn "*ror3_insn" - [(set (match_operand:GPI 0 "register_operand" "=r") - (rotatert:GPI - (match_operand:GPI 1 "register_operand" "r") - (match_operand:QI 2 "aarch64_reg_or_shift_imm_" "rUs")))] + [(set (match_operand:GPI 0 "register_operand" "=r,r") + (rotatert:GPI + (match_operand:GPI 1 "register_operand" "r,r") + (match_operand:QI 2 "aarch64_reg_or_shift_imm_" "r,Us")))] "" - "ror\\t%0, %1, %2" - [(set_attr "type" "shift_reg")] + "@ + ror\\t%0, %1, %2 + ror\\t%0, %1, %2" + [(set_attr "type" "shift_reg, rotate_imm")] ) AFAIK since the output template for the two alternatives is identical you don't need to specify multiple